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Contributor
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Registered: ‎12-10-2018

AXI VDMA different clocks for input and output streams

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Hi everybody!

I'm going to use AXI VDMA. I have a basic question: Can I use different clock frequencies for input and output streams? For example, I want to use 200 MHz clock for the input stream and 148.5 MHz for the output stream. Is this possible and no data loss will occur if I control the input?

P.S: I know from the pg020 that "the memory map side clock frequency is equal to or greater than the
streaming side clock frequency to achieve required performance." and I will do like this, but my question is about streams separate clocks.

Thanks is advance,

Herman

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Registered: ‎06-16-2017

Hi @hermanfisher1994 ,

Yes, you can use different clocks for stream in/out.

"AXI VDMA provides two clocking modes of operation: asynchronous and synchronous. In async mode VDMA control, MM2S and S2MM Primary datapaths can all run asynchronously from each other. Checking Enable Asynchronous Mode in the Vivado IDE enables this mode and creates five clock domains:

• AXI4-Lite clock domain clocked by s_axi_lite_aclk
• mm2s clock domain on the memory map side clocked by m_axi_mm2s_aclk
• s2mm clock domain on the memory map side clocked by m_axi_s2mm_aclk
• s2mm clock domain on the streaming side clocked by s_axis_s2mm_aclk
• mm2s clock domain on the streaming side clocked by m_axis_mm2s_aclk"

Since your output clock is slower, we expect the frame rate will be slower. This means that the read channel will skip/repeat some frames to avoid writing and reading to/from the same frame.

I don't advise you to use your pixel clock as a clock for the vdma output channel. You may need to use a higher clock and use an axi-stream data FIFO for clock domain crossing.

Good luck,

Hamza

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Registered: ‎06-16-2017

Hi @hermanfisher1994 ,

Yes, you can use different clocks for stream in/out.

"AXI VDMA provides two clocking modes of operation: asynchronous and synchronous. In async mode VDMA control, MM2S and S2MM Primary datapaths can all run asynchronously from each other. Checking Enable Asynchronous Mode in the Vivado IDE enables this mode and creates five clock domains:

• AXI4-Lite clock domain clocked by s_axi_lite_aclk
• mm2s clock domain on the memory map side clocked by m_axi_mm2s_aclk
• s2mm clock domain on the memory map side clocked by m_axi_s2mm_aclk
• s2mm clock domain on the streaming side clocked by s_axis_s2mm_aclk
• mm2s clock domain on the streaming side clocked by m_axis_mm2s_aclk"

Since your output clock is slower, we expect the frame rate will be slower. This means that the read channel will skip/repeat some frames to avoid writing and reading to/from the same frame.

I don't advise you to use your pixel clock as a clock for the vdma output channel. You may need to use a higher clock and use an axi-stream data FIFO for clock domain crossing.

Good luck,

Hamza

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Registered: ‎12-10-2018
Thanks Hamza for your kind help!
But I have one more question about your last paragraph: why do you say that? what are issues that may be occurred in this scenario?
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Registered: ‎06-16-2017

Hi @hermanfisher1994 ,

If you use your pixel clock to drive the output channel of the VDMA, you will need a continuous feed from the VDMA, since pixel clock assumes all transactions are valid during one video line (tvalid and tready must be high during a line time). It's not sure that the VDMA will provide that at the exact pixel clock.

To be safe, use a higher clock for the VDMA output channel, and use a FIFO for buffering and for clock domain crossing.

Good Luck,

Hamza

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Registered: ‎12-10-2018
Thanks again Hamza!
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