06-05-2018 11:09 PM
In one of my project , i am using AXI VDMA to process the video frames. I have connected Read/Write Channel Clocks of the VDMA to 200 MHz.So the Read/Write operation is based on 200MHz only. Even though i am getting timing violation inside the AXI VDMA Path.
How to solve this issue?
I have attached timing report and design pdf.
In design pdf
FCLK_CLK2 37.125MHz (output resolution clock for HD@30fps)
06-06-2018 12:17 AM
06-07-2018 02:17 AM
How to generate timing report after synthesis?
In Reports column , route timing summary is only visible.
06-07-2018 03:56 AM
What happen if you use a slower clock for the AXI4S interface of the VDMA?
06-07-2018 06:46 AM
Before I used two clocks in AXI VDMA . The 200MHz for Read Channel and 37.625MHz(Video Clock HD@30fps) for Write Chennel. But i had big timing violation. So i connected 200MHz to Read and Write Channel.
06-08-2018 01:42 AM
06-14-2018 01:24 AM
06-14-2018 11:03 PM
i am not able to upload the project. It is 133Mb. But the maximum size of upload size is around 20 Mb.
06-19-2018 07:45 AM
I sent you a email last week to upload your project but I didn't receive any files back. Did you get the email?
Do you have any progress?
06-21-2018 09:18 AM
If you change the memory map address width in the VDMA it should help meeting timing. Also make sure to use the max burst size.
06-28-2018 07:23 AM
What is your status on this? Were you able to make progress?