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Adventurer
Adventurer
2,143 Views
Registered: ‎03-08-2018

AXI VDMA timing violation issue

Hi,

 

    In one of my project , i am using AXI VDMA to process the video frames. I have connected Read/Write Channel Clocks of the VDMA  to 200 MHz.So the Read/Write operation is based on 200MHz only. Even though i am getting timing violation inside the AXI VDMA Path.

 

How to solve this issue?

 

I have attached timing report and design pdf.  

 

In design pdf   

FCLK_CLK0 50MHz

FCLK_CLK1 200MHz

FCLK_CLK2 37.125MHz (output resolution clock for HD@30fps)

 

Thanks,

kannan

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Moderator
Moderator
2,125 Views
Registered: ‎11-09-2015

Re: AXI VDMA timing violation issue

Hi @kannan,

 

Could you share the timing repport after synthesis?


Florent
Product Application Engineer - Xilinx Technical Support EMEA
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Adventurer
Adventurer
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Registered: ‎03-08-2018

Re: AXI VDMA timing violation issue

Hi,

 

 

      How to generate timing report after synthesis?

      In Reports column , route timing summary is only visible. 

 

 

Thanks,

kannan

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Adventurer
Adventurer
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Registered: ‎03-08-2018

Re: AXI VDMA timing violation issue

Hi,

 

  I have attached the screen shot of the timing violation after synthesis.

 

 

Thanks,

kannan

timingreport1.png
timingreport2.png
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Moderator
Moderator
2,053 Views
Registered: ‎11-09-2015

Re: AXI VDMA timing violation issue

Hi @kannan,

 

What happen if you use a slower clock for the AXI4S interface of the VDMA?

 

Regards,


Florent
Product Application Engineer - Xilinx Technical Support EMEA
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Adventurer
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2,043 Views
Registered: ‎03-08-2018

Re: AXI VDMA timing violation issue

Hi,

 

   Before I used two clocks in AXI VDMA . The 200MHz for Read Channel and 37.625MHz(Video Clock HD@30fps) for Write Chennel. But i had big timing violation. So i connected 200MHz to Read and Write Channel. 

 

Thanks,

Kannan

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Moderator
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Registered: ‎11-09-2015

Re: AXI VDMA timing violation issue

Hi @kannan,

 

Could you share your project?

 

Thanks,

 


Florent
Product Application Engineer - Xilinx Technical Support EMEA
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Registered: ‎11-09-2015

Re: AXI VDMA timing violation issue

HI @kannan,

 

Any update on this? Could you share your project?


Florent
Product Application Engineer - Xilinx Technical Support EMEA
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Adventurer
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Registered: ‎03-08-2018

Re: AXI VDMA timing violation issue

Hi,

 

i am not able to upload the project. It is 133Mb. But the maximum size of upload size is around 20 Mb.

 

Thanks,

Kannan

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Moderator
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Registered: ‎11-09-2015

Re: AXI VDMA timing violation issue

HI @kannan,

 

I sent you a email last week to upload your project but I didn't receive any files back. Did you get the email?

 

Do you have any progress?


Florent
Product Application Engineer - Xilinx Technical Support EMEA
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Moderator
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Registered: ‎11-09-2015

Re: AXI VDMA timing violation issue

Hi @kannan,

 

If you change the memory map address width in the VDMA it should help meeting timing. Also make sure to use the max burst size.

 

Regards,


Florent
Product Application Engineer - Xilinx Technical Support EMEA
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Registered: ‎11-09-2015

Re: AXI VDMA timing violation issue

HI @kannan,

 

What is your status on this? Were you able to make progress?

 

Thanks,


Florent
Product Application Engineer - Xilinx Technical Support EMEA
**~ Don't forget to reply, give kudos, and accept as solution.~**
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