AXI4-Stream to Video

[emotal]

I put an 'AXI4-Stream to Video' IP on my design.

Is this causing problems if vtg_hblank and vtg_hsync are identical, and also vtg_vblank and vtg_vsync are identical?

What I need is Camera-Link signal format.

So, what I did is

    data_valid is connected to vtg_act_vid,

    line_valid is connected to vtg_hblank and vtg_hsync,

    frame_valid is connected to vtg_vblank and vtg_vsync.

Actually, This was working with Vivado 2015.2 ('AXI4-Stream to Video' IP version was 3.0), although I got 'locked' signal high after first two frames.

But when I moved to Vivado 2017.2 ('AXI4-Stream to Video' IP version is 4.0), I cannot not get 'locked' signal high. It is just being low. The IP never got synchronized.

So, my design is wrong? or 'AXI4-Stream to Video4.0' has internal bugs?

Please, help me

Best regards,

[florentw]

Hi @emotal,

Did you check my Video Series about debugging the AXI4-Stream to video out IP? I tried to cover the cases when you do not get the locked signal out of the AXI4S to Video out

[emotal]

florentw, thanks for your reply.

Here are signal waves from my simulations

With AXI4-Stream to Video Out (3.0)) in Vivado 2015.2,

With AXI4-Stream to Video Out (4.0)) in Vivado 2017.2,

Above are from same designs, only differences are AXI4-Stream to Video Out IP's version and Xilinx Vivado's version.

You can see that locked signal is high (in purple box) from first image, but the second image does not have it.

From the second image, I can see AXI4-Stream to Video Out's status.

Below image is shows that the IP status is "000C0006" after "000C0004", which is "Wait for VTG SOF" and "Wait for FIFO SOF".

I cannot understand why I got "wait for SOF" because the start of frame signal (tuser) is given, and vtg_vsync and vtg_vblank are given.

Any idea?

[emotal]

I want to add some.
AXI4-Stream to Video Out's FIFO depth is 1024.
And Hysteresis Level is 12.
And Timing Mode is Master.

[florentw]

Hi @emotal,

Could you try to run the simulation a bit longer. As per PG:

In master timing mode, the latency is generally a function of the FIFO size, if pixels are supplied on the AXI4-Stream bus at the output video rate or higher. 
The latency is relatively steady at approximately FIFO Size - 10 video clocks.

Also, you frame size is really small (and smaller than the FIFO size). I am not sure what results to expect in this case. Will it be you real system (small lines?)

[emotal]

Actual frame size is 256x256, but I reduced the size for these simulations (above ones). 

Does this matter? The AXI4 clock and Video clock are same, not different.

And there were three more frame signals, but I cut the image to be fit on this board.

The cut image has no differences and no signal changes. just same signals were going..

Regards,

[florentw]

HI @emotal,

I would try an image size of at least 64*64 even if I do not think it really matter.

Did you try to simulate for a bit longer? Wait at least 15 frames

[emotal]

Yes, I tried.

I set 64*64 for the image size, and simulation time was long enough to be seen 15 frames.

But the result was same. No video output signals and no locked signal.

I'm going to stop using this IP for now, and I would make my own module.

I do not understand this because previous version was working...

Thanks florentw for your comment so far.

Best regards,

[florentw]

Hi @emotal,

Could you send your test case? I can have a closer look.

[emotal]

How can I send you my files? not on this board. Can you give me your email?

[florentw · Accepted solution]

Hi @emotal,

After analyzing you project, I think you are mainly blocked by the following condition:

I moved the reset of your timing generator to have the vsync generated just after the tuser.

I also believe that there is some improvements to do with your custom timing generator. I had to change its behaviour while reseted.

I do not have much time to investigate further on your issue however with the 2 modified files I sent you, you will have a (kind of) working project to help you understand the issue.

My main recommendation is to use the AXI4-Stream to Video Out in slave mode (controlling the ce of the VTC) with the Xilinx VTC which could simplify your project.

Hope that helps,

Best Regards,

[florentw]

Hi @emotal,

Did you check the file I sent you? does it help?

[emotal]

Hi florentw,

First of all, sorry for late response.

And I solved this problem.

This issue is not from FIFO length of the AXI4Strem to Video Out IP, but from the polarity of vertical sync signal.

I got a hint from your fixed code of mine.

The vertical sync should be opposite polarity and at least one clock earlier than the first line valid signal.

So the IP is now working as I want.

Thank you for your help.