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Adventurer
Adventurer
258 Views
Registered: ‎04-11-2019

About CSI-2 IntraLane mismatch

What's CSI-2 maximum mismatch between P/N for the lane ? Seems standard directly say about InterLane mismatch only ( < UI/50).

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Xilinx Employee
Xilinx Employee
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Registered: ‎03-30-2016

Hello @olkhramus 

MIPI D-PHY spec does not mention any restriction on Intra-Lane limitation.
But the spec define the worst-case of EyeDiagram that should be feed into RX receiver.
Please ensure your system can achieve this.
MIPI_receiver_EyeMask.png

We have received similar question in the past. Xilinx suggest to make less than +/-2ps. See also UG583 Chapter 5.
UG583.png


Regards
Leo

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Xilinx Employee
Xilinx Employee
116 Views
Registered: ‎03-30-2016

Hello @olkhramus 

Do you have any update on this ?
If you feel your questions already answered,
Please kindly marked this thread as Solved, so others can learn from your experience ?

Thanks & regards
Leo

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