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hojze
Observer
Observer
5,231 Views
Registered: ‎05-26-2010

About reset for system generator ?

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Hi,all

    I built a block by using systemgenerator, while it's a subsystem of my project.  And I found out that the block should work when an enable signal depended on the design is given. So an enable signal should be used to control the working state  of  the block. Does systemgenerator have this function, and how to implement it, and  can systemgenerator offer a reset signal for the block  generated.

   Note, there are two signals ce and ce_clr. It seems both of them only have something to do with sampling time of input signals, and they don't control the state of other components in the block.

  Did anyone ever meet this problem, or, any suggestions? Thank you very much.

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ywu
Xilinx Employee
Xilinx Employee
5,790 Views
Registered: ‎11-28-2007

No, you can't set a global reset for the block if that reset signal is not already connected to the rst input on individual sub-blocks in your block.

Cheers,
Jim

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ywu
Xilinx Employee
Xilinx Employee
5,213 Views
Registered: ‎11-28-2007

Most if not all of sysgen blocks have optional rst and en inputs. You need to open the properties window of a block and check the boxes for rst and en. As an example, the snapshot below is for "Register" block:

 

 

Cheers,
Jim
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hojze
Observer
Observer
5,199 Views
Registered: ‎05-26-2010

Thanks Jim for the reply. What I really want to know is after I finished a big block, Can I set a global reset for this block ? And in the block,  the reset or enable optional ports of some basic components like counter, register, etc, have been used to my control my design.

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ywu
Xilinx Employee
Xilinx Employee
5,791 Views
Registered: ‎11-28-2007

No, you can't set a global reset for the block if that reset signal is not already connected to the rst input on individual sub-blocks in your block.

Cheers,
Jim

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