I'mtrying to put an AccelDSP design into a System Generator model. I've done this by exporting it from AccelDSP to the library of System Generator. But whhen I try to simulate it it shows me this error:
'Block requires all inport rates to be the same or constant. The rates are set to: Port sample: 1.#INF'
I've set the Simulink period to 1 and the clock period to 20 ns, but I don't know how to set the port rates to a constant. I don't knoq if it has to be done on AccelDSP or in Simulink.