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pfmiaja
Newbie
Newbie
4,698 Views
Registered: ‎05-22-2008

Accel DSP block in System Generator

Hi:

 

I'mtrying to put an AccelDSP design into a System Generator model. I've done this by exporting it from AccelDSP to the library of System Generator. But whhen I try to simulate it it shows me this error:

 

'Block requires all inport rates to be the same or constant.  The rates are set to:
Port sample: 1.#INF'

 

I've set the Simulink period to 1 and the clock period to 20 ns, but I don't know how to set the port rates to a constant. I don't knoq if it has to be done on AccelDSP or in Simulink.

 

Can you give me some advice?

 

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sandeep.ism
Contributor
Contributor
4,673 Views
Registered: ‎05-22-2008

well i am also having a similar problem with the blocks created using AccelDSP

i got error saying:  "error undriven input port "

although all the input port are connected and all input to the xilinx blocks are though xilinx block

 

wating for words of knowledge....

 

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