Bug axi_vdma 6.3 (Rev. 6) in async mode - Timing failure because false path settings are not generated

[ks-rl]

Overview

With Xilinx Vivado v2018.2+3 the axi_vdma IP cannot be used in async mode with independent clocks.
There required false path settings are missing, leading to unfixable timing failures.

Affected Versions

• Xilinx Vivado v2018.3, axi_vdma version 6.3 (Rev. 6)
• Xilinx Vivado v2018.2, axi_vdma version 6.3 (Rev. 5)
• Last known working version: Xilinx Vivado v2017.2
• Other versions inbetween could be also affected.

Details

With the same IP settings, different XDC files are created.
Correct is v2017.2 (left), wrong is v2018.3 (right):

The reason is a wrong statement in $XILINX_VIVADO/data/ip/xilinx/axi_vdma_v6_3/ttcl/xdc.ttcl
Correct is v2017.2 (left), wrong is v2018.3 (right):

Hotfix

Apply the following patch to the file $XILINX_VIVADO/data/ip/xilinx/axi_vdma_v6_3/ttcl/xdc.ttcl (make a backup)
--- /opt/xilinx_vivado/Vivado/2018.3/data/ip/xilinx/axi_vdma_v6_3/ttcl/xdc.ttcl.org    2019-01-17 07:17:24.932690880 +0100
+++ /opt/xilinx_vivado/Vivado/2018.3/data/ip/xilinx/axi_vdma_v6_3/ttcl/xdc.ttcl    2019-01-17 07:18:25.964742551 +0100
@@ -12,7 +12,9 @@
 <: set enable_all [getBooleanValue "c_enable_debug_all"] :>
 <: set enable_bram [getBooleanValue "c_enable_debug_info_1"] :>
 <: set enable_s2mm_bram [getBooleanValue "c_enable_debug_info_9"] :>
-<: set enable_fifo_xdc 0 :>
+# 2019-01: Hot-Fix for async VDMA constraints generation
+# <: set enable_fifo_xdc 0 :>
+<: set enable_fifo_xdc 1 :>
 <: if {(($c_family != "kintex7" && $c_family != "virtex7" && $c_family != "artix7" && $c_family != "zynq" && $c_family != "spartan7"))} { :>
 <: set is_us_device 1 :>
 <: } else { :>

Complete file is attached.

 Please note that I don't know whether this hotfix has any side-effects. It did worked for my case, which of course doesn't mean it works also for you :-)

[florentw]

HI @ks-rl,

Thank you for sharing. We might need to investigate this. Could you share a test case showing the timing failure?

Regards,

[florentw]

Hi @ks-rl,

In fact I was able to reproduce a timing issue which seems to be due to a lack of constraint so to the same root casue as you are experiencing.

I am investigating on this.

Regards,

[ks-rl]

Hi Florent,

Please find attached a test case exhibiting this behaviour.

You can run it with the following steps

1. Extract file axi_vdma_async_failure.tar.bz2 into new directory
2. Start vivado
3. Tcl: source recreate.tcl
4. Run Synthesis
5. Open synthesized design
6. Report timing summary

[florentw]

HI @ks-rl,

Thank you for the test case. As I was already able to reproduce the issue, I already discussed this with development. They confirmed that this is an issue (not that this change was introduce in 2017.3 so all version from 2017.3 to 2018.3 are affected).

Caution: The fix you are mentioning is correct ONLY for built-in fifo for for 7-series devices and not for others.

This should be fixed in the next vivado release. I would recommend the user to write the constraints directly in the main xdc file for the project as workaround.

Best Regards,

[florentw · Accepted solution]

Hi @ks-rl,

Thanks again for reporting this issue and sharing your solution.

I just wrote AR#71984 to document the issue and the recommended workaround.

As mentioned this should be fixed in the next vivado release.

Best Regards,