cancel
Showing results for 
Show  only  | Search instead for 
Did you mean: 
francocapraro12
Adventurer
Adventurer
596 Views
Registered: ‎09-27-2018

CLK for SDI Tx (148.5MHZ) in Ultrazed EV SOM+CC

Hello. Im trying to implement a SDI TX using SMPTE UHD-SDI TX SUBSYSTEM and UHD-SDI GT in UltraZed -EV SOM + CC.
I have some doubt about the CLK used.

 

pastedImage_0.png

 

This is my connection block. I read that a 148.5 CLK is needed, Seeing the User Guide  of CC, its says:

"Clock Generator 2 – U6, IDT 8T49N241-048NLGI....

....

...

Default output frequencies:

– Output 0 – 100 MHz, HCSL, 3.3V, PCIe_REFCLK to PCIe port connector J14 with 33 ohm series termination resistors.

 Output 1 – 148.5 MHz, LVDS, 3.3V, AUX/Loopback, JX2 GTH_REFCLK[5]" PAGE 46

 

This is (in the XDC file

set_property PACKAGE_PIN J7  [get_ports {GTH_REFCLK5_N}]

set_property PACKAGE_PIN J8  [get_ports {GTH_REFCLK5_P}]

But MY QUESTION IS:
This clk need to be the "CLK_IN_D" input  of the Utility Buffer and the Input for intf_0_qpll_refclk_in or intf_0_sb_tx_clk ?

Im using  this https://forums.xilinx.com/t5/Design-and-Debug-Techniques-Blog/Video-Blog-Implementing-the-UHD-SDI-TX-subsystem-in-a-TX-only/ba-p/1170471
as guide and VCU https://xterra2.avnet.com/xilinx/zedboard/ultrazed-ev/vcu-trd-ports/rdf0428-uz7ev-vcu-trd-2019-2 as my project.

Also i want to know the next step to configure the SDI TX subsystem in Vitis ( Im also using a Video Test Pattern Generator working good and configured in Vitis)

Best,
Franco

0 Kudos
7 Replies
ashokkum
Moderator
Moderator
536 Views
Registered: ‎04-09-2019

Hello @francocapraro12 ,

Yes, the reference clock will source to the utility buffer and the output clock from the buffer will feed to the intf_x_refclk_in. I would recommend you to refer our passthrough example design to know the configurations of RX and TX subsystems.

With Regards,

Ashok.

0 Kudos
francocapraro12
Adventurer
Adventurer
529 Views
Registered: ‎09-27-2018

Hi @ashokkum , thank you for your time.
I will see the passthrough example to see how config with de PS part. My last question is about the value of the CLK. The Uz7-EV CC User Guide (PAGE 46) says:
"
Default output frequencies:
– Output 0 – 100 MHz, HCSL, 3.3V, PCIe_REFCLK to PCIe port connector J14 with 33 ohm
series termination resistors.
– Output 1 – 148.5 MHz, LVDS, 3.3V, AUX/Loopback, JX2 GTH_REFCLK[5]
– Output 2 – 250 MHz, LVDS, 3.3V, 3G-SDI, JX2 GTH_REFCLK[2]
– Output 3 – 148.5 MHz, LVDS, 3.3V, HDMI, JX2 GTH_REFCLK[0] "

The CLK needed is 148.5MHz but the Output 2 says "3G-SDI" and 250MHz, so im confused about the value of the CLK.
EDIT:
I couldnt find the Steps to configure the SDI TX IP in VITIS. Someone know some guide ?

Best,
Franco

0 Kudos
ashokkum
Moderator
Moderator
463 Views
Registered: ‎04-09-2019

Hello @francocapraro12 ,

The external oscillator (SI chips) on the board needs to be configure for 148.5Mhz for a reference clock frequency. Regarding the IP configuration, You have to use the UHD-SDI GT IP GUI to configure the line rate and clocks information. Through TX subsystem GUI, you can configure the interface, PPC and color format details. For this, I don't think so you need software drivers to use.

With Regards,

Ashok.

0 Kudos
francocapraro12
Adventurer
Adventurer
458 Views
Registered: ‎09-27-2018

Hi @ashokkum ,
Im using Ultrazed EV SOM+CC, not ZCU106, so im trying to use the  "– Output 1 – 148.5 MHz, LVDS, 3.3V, AUX/Loopback, JX2 GTH_REFCLK[5]".

When you say  "UHD-SDI GT IP GUI to configure.:". I use this config:

francocapraro12_0-1622548928087.png

 

Can i share my project here with you ?
Best,
Franco

EDIT:
If I see cmp_gt_sts in ILA:

francocapraro12_0-1622550536405.png


So:


QPLL0  IS NOT LOCKED
tx_change_done. Link 0 GT TX configuration is success
rx_change_done. Link 0 GT RX configuration is success

 

Spoiler
 

 

0 Kudos
ashokkum
Moderator
Moderator
407 Views
Registered: ‎04-09-2019

Hello @francocapraro12 ,

I understand you are using Ultrazed EV board from avnet, Which had Zynq UltraScale+ MPSoC FPGA in baground. So, give me a day time. I will dig in more. Meanwhile, can I get the register space details of the TX subsystem.  Also, could you please let me know the baground of the video data sources, which are providing video data as input to the TX sub system.

With Regards,

Ashok.

0 Kudos
francocapraro12
Adventurer
Adventurer
382 Views
Registered: ‎09-27-2018

Hi @ashokkum ,

Thank you again for your time. I will add the info.
I was not sure about the Register Space details, so i will add the block design, xdc and the config.

francocapraro12_0-1622785924596.png

 


Im using a TPG as video input for SDI TX. The config of the TPG is good because i can see with ILA the signals.

francocapraro12_1-1622786439445.png

SDI TX and SDI GT :

francocapraro12_2-1622786531461.png

 

 

This is the Config for the TPG and SDI TX in Vitis:

 

 

 

 

	    	u32 height,width,status;
	    	XV_tpg_DisableAutoRestart(&ptpg);
	    	status = XV_tpg_IsReady(&ptpg);
	    	printf("Status %u \n\r", (unsigned int) status);
	    	status = XV_tpg_IsIdle(&ptpg);
	    	printf("Status %u \n\r", (unsigned int) status);
	    	XV_tpg_Set_height(&ptpg, (u32)1080);
	    	XV_tpg_Set_width(&ptpg, (u32)1920);
	    	height = XV_tpg_Get_height(&ptpg);
	    	width = XV_tpg_Get_width(&ptpg);
	    	XV_tpg_Set_colorFormat(&ptpg,XVIDC_CSF_YCRCB_422);
	    	//XV_tpg_Set_maskId(&ptpg, 0x0);
	    	//XV_tpg_Set_motionSpeed(&ptpg, 0x4);
	    	printf("info from tpg %u %u \n\r", (unsigned int)height, (unsigned int)width);
	    	XV_tpg_Set_bckgndId(&ptpg, XTPG_BKGND_COLOR_BARS);
	    	status = XV_tpg_Get_bckgndId(&ptpg);
	    	XV_tpg_Set_ovrlayId(&ptpg, 0);
	    	printf("Status %x \n\r", (unsigned int) status);
	    	XV_tpg_EnableAutoRestart(&ptpg);
	    	XV_tpg_Start(&ptpg);
	    	xil_printf("PTG START TX\n\r");
	    	//status = XV_tpg_IsIdle(&ptpg);
	    	//printf("Status %u \n\r", (unsigned int) status);
	    	//printf("INFO from tpg %u %u \n\r", (unsigned int)StreamPtr->Timing.VActive, (unsigned int)StreamPtr->Timing.HActive);
	    	xil_printf("Enable TX Video Bridge\r\n");

Status = SdiTxSs_SelfTestExample(XV_SDITXSS_DEVICE_ID);
	if (Status != XST_SUCCESS) {
		xil_printf("SDI TX Subsystem self test example "
			"failed\n\r");
		return XST_FAILURE;
	}

	xil_printf("/* Initialize SDI TX Subsystem */\n\r");
	XV_SdiTxSs_ConfigPtr = XV_SdiTxSs_LookupConfig(XPAR_XV_SDITXSS_0_DEVICE_ID);

	XV_SdiTxSs_ConfigPtr->BaseAddress = XPAR_XV_SDITXSS_0_BASEADDR;
	if (!XV_SdiTxSs_ConfigPtr) {
		SdiTxSs.IsReady = 0;
		return XST_DEVICE_NOT_FOUND;
	}
	Status = XV_SdiTxSs_CfgInitialize(&SdiTxSs,
				XV_SdiTxSs_ConfigPtr,
				XV_SdiTxSs_ConfigPtr->BaseAddress);
	if (Status != XST_SUCCESS) {
		xil_printf("ERR:: SDI TX Initialization failed %d\r\n", Status);
		return XST_FAILURE;
	}
	ConfigureTx();
	xil_printf("CONFIGURE TX\n\r");
	    	xil_printf("STREAMSTART TX\n\r");
	    	XV_SdiTxSs_StreamStart(&SdiTxSs);

 

 

 

 

 

0 Kudos
francocapraro12
Adventurer
Adventurer
302 Views
Registered: ‎09-27-2018

Hi @ashokkum , 

Do you have some news ? 
Best,
FC

0 Kudos