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saipradeep523
Observer
Observer
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Registered: ‎02-18-2019

CSI-2 Rx Capture Pipeline integration with IIO framework drivers with ADI DMA instead of framebuffer write

Hi 

I am working on the IMX274 Camera Sensor with MIPI CSI-2 Rx Pipeline as shown in the diagram. In the pipeline the FPGA IPs used is MIPI CSI-2 RX, demosaic , Gama, VPSS Scalar, VPSS CSC and Frame buffer write. my requirements demands IIO drivers integration with ADI DMA instead of Frame buffer write IP.

All these Xilinx FPGA IP drivers are registering with XVIPP driver, this driver is creating V4L- Sub devices video* and media device files  if the DMA is mapped in dts (If DMA field is not mapped it is not creating the all these device files). Driver path: drivers/media/platform/xilinx/xilinx-vipp.c and its dts is as follows:

vcap_gmsl {
compatible = "xlnx,video";
dmas = <&fb_wr_csi_0 0>;
dma-names = "port0";

ports {
#address-cells = <1>;
#size-cells = <0>;

port@0 {
reg = <0>;
direction = "input";

vcap_gmsl_in0: endpoint {
remote-endpoint = <&v_scaler_0_out>;
};
};
};
};

Can we replace DMA filed 'dmas = <&fb_wr_csi_0 0>;' with ADI DMA. While i am doing experiments it is hanging.

ADI DMA dts:

axidma: axidma@0 {
#dma-cells = <0x1>;
compatible = "adi,axi-dmac-1.00.a";
reg = <0x0 0xb0040000 0x0 0x10000>;
interrupts = <0x0 90 0x4>;
clocks = <&axi_stream_clk>;

adi,channels {
#address-cells = <0x1>;
#size-cells = <0x0>;

dma-channel@0 {
reg = <0x0>;
adi,source-bus-width = <32>;
adi,source-bus-type = <1>;
adi,destination-bus-width = <64>;
adi,destination-bus-type = <0>;
adi,length-width = <24>;
};
};
};

Another Question is 

2) I want to completely replace XVIPP driver with my own IIO driver wrapper on top of IIO driver. I experimented but in this case the v4l sub devices, video and media device files are not creating. is it possible to map data path at least? 

XXIPP_Driver_flow.png
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2 Replies
florentw
Moderator
Moderator
363 Views
Registered: ‎11-09-2015

Hi @saipradeep523 

The AXI DMA does not handle the Video information (start of frame, end of line), so I am not sure how that would integrate with the driver.

What is the reason why you are not using the video frame buffer as DMA? This is, with the AXI VDMA, the only supported configuration by Xilinx


Florent
Product Application Engineer - Xilinx Technical Support EMEA
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saipradeep523
Observer
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Registered: ‎02-18-2019

My target is integration of  LIBIIO with capture pipeline either with ADI DMA or Video frame buffer as DMA.

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