hi experts.I want to know if there is any simulation file format save signals accordding to every clock's rising edge.if so, i could read the signals out with MATLAB to be processed,for example FFT,or verified.Thanks.
When you generate HDL for a System Generator design you can select "Create Testbench" which will create text files which log the stimulus which drives the gateway in blocks as well as aa testbench which reads these in and a ModelSim .do script to excecute the HDL simulation.
Otherwise, in Simulink there are many blocks that can be used to capture data such as the scope or To Workspace blocks which allows you to save the simulation data as a workspace variable.
The clock is inferred based on the periods set and is not stored in a file however there is a Clock Probe under Xilinx Blockset > Tools that allows you to see the clock signal in the Simulink simulation as well.
I use System Generator 9.2i and this is my experience:
I don't use the matlab outputs at all (excluding to/from workspace if I need them for a second simulation). I use the WaveScope token in my design (Open your library browser then choose: Xilinx Blockset> Tools> WaveScope) Double click on this and then select your nets. It will automatically add your clock. Then run your simulation and you have a simulation! You will probably want to change the recording limits so you can see more than 10 cycles also.
One issue with WaveScope is that if you have more nets the menu isn't scrollable and you cannot select all of your nets. To get around this I do 2 things: 1) change the names so you force a blocks nets to the top of the list and 2) I setup my dual monitors to act like they are stacked instead of side by side so the menu can be as long as both monitors are high.
The quirks take some getting used to but I think it ends up being much easier to simulate than exporting into model sim or NCsim. I'd say you can use it for blocks in your design but stay away from having to simulate too large of a design.