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zhanyan110
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Registered: ‎09-25-2018

Can't enable command mode for MIPI DSI Subsystem IP.

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Hi experts,

I use MicroBlaze core to initial MIPI DSI IP. I want to use command mode for initial peripheral OLED screen. After I set bit3 enable to CCR register(0x00), and then read CCR register(0x00) and STATUS register(0x2C), the bit3 of CCR is still zero, and the bit6 and bit7 of STATUS(0x2C) is still zero. what's the possible reason ?

the controller ready bit is high, and the core enable bit is low.

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karnanl
Xilinx Employee
Xilinx Employee
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Registered: ‎03-30-2016

Hello @zhanyan110 

DCS Long packet is supported from 2019.2.
Please upgrade your Vivado version.

DCS_LONG_2019.2_supported.png

Regards
Leo


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karnanl
Xilinx Employee
Xilinx Employee
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Registered: ‎03-30-2016

Hello @zhanyan110 

Did you provide a stable 200MHz clock to dphy_clk_200M pin ?
Did you reset the IP correctly ? (See also PG238 Chapter3)
Did you enable the core ? ( Please see bit[0] below )
REG_DS238.png

Please share your register dump, so I can double check the value for you.

Thanks
Leo


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zhanyan110
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Registered: ‎09-25-2018

Hi karnanl,

 

Do I need set the timing register before I use command mode for long packet command ?

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karnanl
Xilinx Employee
Xilinx Employee
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Registered: ‎03-30-2016

Hello @zhanyan110 

I believe configuring the timing registers are not necessary for sending long packet command.

Thanks
Leo


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zhanyan110
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Registered: ‎09-25-2018

Did you provide a stable 200MHz clock to dphy_clk_200M pin. ---- YES

Did you reset the IP correctly. ---- YES

Here is my C code, and the result, please help me check. 

C code is 1.PNG

the result is 2.PNG

1.PNG
2.PNG
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karnanl
Xilinx Employee
Xilinx Employee
645 Views
Registered: ‎03-30-2016

Hello @zhanyan110 

1. According to Status Register ( Address 0x2C == 0x20 )
   It seems that the MIPI DSI TX is not ready to accept any Long/Short Packet.

2. Please follow the procedure stated in PG238 to enable command mode.
    I believe the Core Configuration Register is "0x04",
    So Core is not enabled, and DSI is in Video mode.

ENABLING_DSI.png

Thanks
Leo


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zhanyan110
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Registered: ‎09-25-2018

Hi karnanl,

I modify the C code as below ( picture1 ).

After I enable bit3 and bit0 in CCR register, the CCR value readback is still video mode. and the Status Register is still not ready to accept any Long/Short Packet.

1.PNG
2.PNG
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karnanl
Xilinx Employee
Xilinx Employee
625 Views
Registered: ‎03-30-2016

Hello @zhanyan110 

What is your Vivado version ? Could you please share your XCI ?
Is the "DCS Command Mode" enabled ?
DCS_COMMAND_ENABLED.png

Thanks
Leo


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zhanyan110
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Registered: ‎09-25-2018

I have tried vivado2018.3 and 2019.1, both met the same issue.

It seems my IP version is v2.0, there is no option "DCS command mode".

 

1.PNG
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karnanl
Xilinx Employee
Xilinx Employee
610 Views
Registered: ‎03-30-2016

Hello @zhanyan110 

DCS Long packet is supported from 2019.2.
Please upgrade your Vivado version.

DCS_LONG_2019.2_supported.png

Regards
Leo


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zhanyan110
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Registered: ‎09-25-2018

After I upgrade to Vitis 2020.1. I can see the option "DCS command mode".

But  a new problem happen. When I run debug the C code with "XDsiTxSs_CfgInitialize(&DsiInstance,DsiConfigPtr,DsiConfigPtr->BaseAddr);"

the program will jump to line 244 in xdphy.c at the beginning. It is very weird.

zhanyan110_0-1597298489027.png

zhanyan110_1-1597298572926.png

 

 

karnanl
Xilinx Employee
Xilinx Employee
525 Views
Registered: ‎03-30-2016

Hello @zhanyan110 

>After I upgrade to Vitis 2020.1. I can see the option "DCS command mode".

Okay that is good to hear.

>But a new problem happen. When I run debug the C code with "XDsiTxSs_CfgInitialize(&DsiInstance,DsiConfigPtr,DsiConfigPtr->BaseAddr);"
>the program will jump to line 244 in xdphy.c at the beginning. It is very weird.

Why you are using D-PHY driver ? I don't think it is necessary for DSI TX...

Regards
Leo


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zhanyan110
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Registered: ‎09-25-2018

I didn't use D-PHY driver. the core-program seems run fly with XDsiTxSs_CfgInitialize(&DsiInstance,DsiConfigPtr,DsiConfigPtr->BaseAddr);

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karnanl
Xilinx Employee
Xilinx Employee
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Registered: ‎03-30-2016

Hello @zhanyan110 

Tried to read the DSI driver. It seems in 2020.1 XDsiTxSs_Activate() has been modified.
Now the function also enable/disable sub-cores, when calling XDsiTxSs_Activate().
enabe_disable_subcores.png

So, that's is why XDsiTxSs_Activate() , will also activate D-PHY. (XDphy_Activate)
activate_dphy.png


I hope this clarify your question.

Kind regards
Leo


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zhanyan110
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Registered: ‎09-25-2018

karnanl,

Do the DSI IP have read channel for command mode ?

For example, If I want to read register value from the OLED displayer(peripheral device) to FPGA, how to do it ?

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karnanl
Xilinx Employee
Xilinx Employee
316 Views
Registered: ‎03-30-2016

Hello @zhanyan110 

Unfortunately Xilinx MIPI DSI TX Subsystem does not support any read command.
DSI_unsupported.png

Kind regards
Leo


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