03-07-2021 02:55 PM - edited 03-07-2021 03:16 PM
I'm having a problem which is described here: https://forums.xilinx.com/t5/Video-and-Audio/ZU3EG-DisplayPort-Training-sequence-and-monitor-wake-up-fails/m-p/1215040
Basically, I have a DisplayPort test design which works great in a Ultra96v2 board (ZU3EG) and fails in a MYIR FZ3 board(ZU3EG).
In the FZ3 board, the terminal outputs shows that it cannot stablish the link.
I have researched a lot, and I think I have found the problem.
This is a part of the schematic of FZ3:
This is a part of the schematic of Ultra96v2:
If you take a look to both pictures to can see that (in FZ3 one) lanes are connected in a direct way:
- Lane 0 (ML_L0_P and ML_L0_N) is connected to lane 0 (MGT3_DP0_TX_P and MGT3_DP0_TX_N)
- Lane 1 (DP) is connected to Lane 1 (GT)
BUT, in Ultra96v2's schematic, you can see they are connected in reverse way:
- Lane 0 (DP) is connected to Lane 1 (GT)
- Lane 1 (DP) is connected to Lane 0 (GT)
So I think is the reason why this design works in Ultra96v2 but fails in FZ3.
Now, my question is: Where should I make this modification? (I am using the Displayport controller of the ZynqUS+)
I think is is something that should be modified in my bare metal application, but I couldn't find any option in the DPPSU driver's header file to modify this: https://github.com/Xilinx/embeddedsw/blob/master/XilinxProcessorIPLib/drivers/dppsu/src/xdppsu.h
I appreciate any help.
Thanks in advance.
03-08-2021 02:03 AM
The way it is connected on the Ultra92 is the correct way as per the ZYNQ MPSoC TRM (UG1085):
I do not think that you can change this in SW.
Is there any reference design of the MYIR FZ3 board using the Displayport output?
In my understanding you will not be able to make it working...
03-08-2021 02:10 AM
Looking at the MYIR FZ3 schematics (http://www.myirtech.com/soft.asp?id=973), it does not seems to match what you are saying:
I see DP0 connected to GT lane 3 and Dp1 connected to GT lane 2 which matches what I have shared from the TRM as well
03-08-2021 03:59 AM
According to your first message, it is clear to me that I will not be able to use the DisplayPort using a bare metal application. But I think I will be able to run it using a Petalinux-based application, am I correct?
I think it is possible to change the lane mapping in the Device Tree.
About your second message, I don't really get it. Could you please explain what you are trying to use? it seems contradictory with your previous message
03-08-2021 04:06 AM
I do not think you will be able to use baremetal or petalinux. This is a physical mapping and I do not think there is any setting to swap the lanes.
From my first message, you can see in the screenshot that there are 2 valid configuration:
DP Lane 1 to GT Lane 0 (GTR) and DP Lane 0 to GT Lane 1 (GTR) (this is what is done on the Ultra96)
DP Lane 1 to GT Lane 2 (GTR) and DP Lane 0 to GT Lane 3 (GTR) (this is what is done on the MYIR FZ3 from the schematic I have found)
What you have on your board (DP Lane 0 to GT Lane 0 (GTR) and DP Lane 1 to GT Lane 1) will not work according to me
03-08-2021 07:16 AM - edited 03-08-2021 07:17 AM
I really appreciate your answer but I do believe that it is possible to make that lane swapping through the Petalinux's Device Tree. I'm saying this because using the stock SD card image from MYIR, I can run applications and see the video output on my screen through DisplayPort.
I can even use "startx" in Petalinux and the see the GUI through DisplayPort.
So, in my opinion, there are 2 ways to fix this:
1- Build again the DPPSU driver making the swap lane.
2- Make that lane swapping in Petalinux like MYIR did in their stock SD image.
Unfortunately, I am not getting any response from MYIR support, so I wonder if can you double check these two possible solutions with your colleagues from the DisplayPort team.
Thanks in advance
03-08-2021 07:56 AM
In fact we were looking at different part of the schematic. I believe you should look at the part I shared which is how the DP lanes are mapped:
DP Lane 1 to GT Lane 2 (GTR) and DP Lane 0 to GT Lane 3 (GTR)
So you need to make sure this is properly configured in the ZynqMPSoC GUI (should be DP dual higher)
03-10-2021 01:11 PM
dual higher configuration does not work neither
If you take a look to this Xilinx's Device tree entry example:
You can see
phys = <&lane1>, <&lane0>; phy-names = "dp-phy0", "dp-phy1";
Do you think this configuration from below could solve the problem?
phys = <&lane0>, <&lane1>; phy-names = "dp-phy0", "dp-phy1";
03-11-2021 01:41 AM
No I do not think so. Again, your understanding of the schematic is incorrect.
You believe that on the MYIR board there is the following mapping: DP Lane 1 to GT Lane 1 (GTR) and DP Lane 0 to GT Lane 0 (GTR)
While I have shown shown you that this is: DP Lane 1 to GT Lane 2 (GTR) and DP Lane 0 to GT Lane 3 (GTR)
If you do not want to believe me and try things on your own just do...