cancel
Showing results for 
Show  only  | Search instead for 
Did you mean: 
Explorer
Explorer
2,291 Views
Registered: ‎08-31-2016

Configuring the VTC Registers in HDMI TX SS

Jump to solution

Hello,

 

How to configure the Video Timing Controller present in the HDMI TX Subsystem?

 

Is there any offset associated with VTC Registers?

 

Regards,

Vinay 

Vinay Shenoy
0 Kudos
Reply
1 Solution

Accepted Solutions
Xilinx Employee
Xilinx Employee
2,269 Views
Registered: ‎08-02-2007

@sreejitht

 

As per documented in PG235,

IMPORTANT: The direct register level access to any of the submodules is not supported.

 

When you use AXI4 STream interface, VTC and AXI4_Stream_to_Video_Out IP is inside HDMI TX Subsystem, in that case the VTC address is not supposed to be expose to the users.

 

That's why I suggest you generate HDMI TX Subsystem IP with native interface, and then add VTC IP manually. In that case, you can get the VTC address from address editor of IPI.

 

 

View solution in original post

0 Kudos
Reply
11 Replies
Xilinx Employee
Xilinx Employee
2,244 Views
Registered: ‎08-02-2007

@vinay_shenoy

 

You can check xparameters.h in bsp to get the VTC offset.

 

If you want to use VTC more flexible, it's better to generate HDMI with native interface, and then add VTC outside of HDMI TX Subsystem IP.

 

 

Observer
Observer
2,220 Views
Registered: ‎02-21-2017

Hi @xud,

 

If we need to configure VTC from petalinux, there how we will get the offset?

The HDMI TX subsystem document not mentioned anything related to VTC address.

 

Thanks,

0 Kudos
Reply
Xilinx Employee
Xilinx Employee
2,270 Views
Registered: ‎08-02-2007

@sreejitht

 

As per documented in PG235,

IMPORTANT: The direct register level access to any of the submodules is not supported.

 

When you use AXI4 STream interface, VTC and AXI4_Stream_to_Video_Out IP is inside HDMI TX Subsystem, in that case the VTC address is not supposed to be expose to the users.

 

That's why I suggest you generate HDMI TX Subsystem IP with native interface, and then add VTC IP manually. In that case, you can get the VTC address from address editor of IPI.

 

 

View solution in original post

0 Kudos
Reply
Observer
Observer
2,191 Views
Registered: ‎02-21-2017

Hi @xud,

 

Actually I'm trying to add one tpg to the HDMI pass-through design which contains HDMI TX Subsystem.

 

The observation I'm seeing after that is, the tpg will be working only for the maximum resolution supported by the monitor.

 

That is 4K monitor will support only TPG with 2160 height and 3840 width, if I set tpg for full hd(1920x1080) or hd(1280x720) the display is not coming in 4k monitor. Same way if we are using full hd monitor, it is showing only full hd tpg.

 

Can you tell how this is happening or how the VTC is getting configured for this ? I need to get Full HD tpg  in 4K Monitor. For that what should I do?

 

 

0 Kudos
Reply
Xilinx Employee
Xilinx Employee
2,182 Views
Registered: ‎08-02-2007

@sreejitht

 

HDMI Passthrough design already contains TPG, where do you put another TPG?

 

If the same design works for full HD monitor, It means the design is capable to send out the correct Video timing.

 

If the issue only occurs when you try to switch between different resolution, we need to check the connect of tx_refclk_rdy.

 

I suspects the issue is related to settings in your 4K monitor. When you don't see image on 4K monitor, can you monitor lock signal of HDMI TX, does it lock or not?

 

What's the model type of your 4k monitor?

0 Kudos
Reply
Observer
Observer
2,171 Views
Registered: ‎02-21-2017

Hi @xud,

 

I'm including the TPG across the HDMI output. Attached the image of design for your reference.

There is 2 frame buffer read and one TPG connected to one switch IP. Then switch O/P is connected to HDMI TX Subsystem.

 

For that new TPG I added new driver code. The driver only configuring TPG registers. There I'm not doing any VTC Configurations.

 

"HDMI Passthrough design already contains TPG" -

I didn't find any TPG in the HDMI passthrough block design. Can you tell me where it is added actually.

 

"I suspects the issue is related to settings in your 4K monitor"

I think there is no problem with monitor. Because it's working fine for other projects.

 

TPG.PNG
0 Kudos
Reply
Xilinx Employee
Xilinx Employee
2,161 Views
Registered: ‎08-02-2007

@sreejitht

 

When I mentioned HDMI example design, is the example design generated by Vivado, you can refer to Chapter 5 of PG235 for detailed flow.

 

Sorry - I didn't realize you were referring the framebuffer example design, which is from Wiki page.

0 Kudos
Reply
Moderator
Moderator
2,020 Views
Registered: ‎11-09-2015

Hi @vinay_shenoy

 

Are the replies from @xud enough for you?

 

If yes, please kindly mark the response which helped as solution (click on "Accept as solution" buton below the reply)

If this is not solved/answered, please reply in the topic giving more information on your current status.

Thanks and Regards,


Florent
Product Application Engineer - Xilinx Technical Support EMEA
**~ Don't forget to reply, give kudos, and accept as solution.~**
0 Kudos
Reply
704 Views
Registered: ‎10-16-2019

Hi Xud,

This is the first time I checked out your enlightening information. You mentioned that the AXI4-stream interface has already integrated the VTC and AXI4_Stream_to_Video_Out and VTC inside it. Why does Xilinx not release a corresponding example revision based on the Native interface? I suppose it is not hard given your claim is true. Could you please offer help here,for example, just bring part of the key points inside AXI4-steram interface out?  I have been working on this issue for months, I guess there would be numerous similar inquies yet to come.

0 Kudos
Reply
699 Views
Registered: ‎10-16-2019

@xud 

Hi Xud,

This is the first time I checked out your enlightening information. You mentioned that the AXI4-stream interface has already integrated the VTC and AXI4_Stream_to_Video_Out and VTC inside it. Why does Xilinx not release a corresponding example revision based on the Native interface? I suppose it is not hard given your claim is true. Could you please offer help here,for example, just bring part of the key points inside AXI4-steram interface out?  I have been working on this issue for months, I guess there would be numerous similar inquies yet to come.

0 Kudos
Reply
Xilinx Employee
Xilinx Employee
205 Views
Registered: ‎08-02-2007

cloudyundezhi@gmail.com 

Example design depends on marketing's decision, you are welcome to provide feedback to your FAE, so he can apply an example request with marketing if needed

0 Kudos
Reply