06-10-2020 06:12 AM - edited 06-10-2020 06:16 AM
Hello. I have designed a system that transfers two images to my custom IP, and delivers two output images to ps by two VDMAs. IP worked well when I tested it on vivado hls, and block design validation and creating bitstream was done without error. But when I ran code on jupyter notebook, I could start readchannels, but failed on writechannels(MM2S) of both VDMAs. I used pynq-z2 board and vivado 2019.1 version.
I think the problem would be :
1. VDMAs are not connected properly.
2. both VDMA's ports(MM2S, S2MM) are mapped to S_AXI_HP0, same address range.
But there could be other problems I don't know.
Any help would be appreciated.
Thanks in advance
06-10-2020 06:29 AM
I would suggest simplifying your design at first and then building it up.
1. Remove the HLS IP and just connect the M_AXIS_MM2S port of the VDMA to the S_AXIS_S2MM port. Verify that you are able to get the VDMA to read data from DDR and write it back to a different location.
2. Once both VDMAs are properly transfering data, add the HLS IP back into the design.
A couple of additional suggestions:
1. Use the System ILA to see what's happening in your design.
2. Keep in mind that the VDMA's "HSIZE" and "STRIDE" values are in bytes not number of pixels.
3. The VDMA expects the AXI4-Stream port from your HLS IP to properly use the Tlast and Tuser signals. Check out UG934
4. If you are new to using video on Xilnx devices, check out the Xilinx Video Series for some good background