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Registered: ‎05-29-2019

DDC issue on HDMI 1.4/2.0 Receiver IP

Hello,

In our board we're using 4 Zynqs, with two HDMI 1.4/2.0 Receiver IP per Zynq.
Totally 8 HDMI Rx inputs per board.
We have an issue on DDC of input 8 of the board.
Therefore EDID and also HDCP tests fail on this input.

After some investigation we discovered that SCL/SDA rising time on this input a slightly higher then on the other ones.
No oveshoot/undershoot are observed at all.
However it's still within the spec of I2C (attached scope shot).

We have register packed in IOB on these signals.
Attached Vivado definitions on these pins (HP bank).

I did not find any parameters to be set regarding IIC controller in hdmi_rx_ss IP.
This is neither in Xilinix HDMI Rx software drivers code or block_design or documentation.
Hdmi_rx_ss IP apparently using 100MHz clock we provided in the block design.
Can you confirm that default parameters of DDC/IIC are for 100MHz ?

Do you have any clue and suggesthions for the wotkaround.

Best regards.
Boris Barak.

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Teacher
Teacher
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Registered: ‎06-16-2013

Hi boris.barak@vitec.com 

 

Would you share your observed wave form ?

I can't find any picture in your post...

 

Best regards,

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Registered: ‎05-29-2019

Hi,

Sorry' I've obviously forgot to attach.

Attached DDC pins properties in Vivado and DDC lines signals, measured next to Zynq.

Boris Barak.

DDC_pads_Vivado.png
scope_DDC_SCL=CH1.jpeg
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