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skaat27
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DISPLAY PORT 1.4 RX Subsystem not working

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Hi All,

I am working on a project that uses the displayport 1.4 RX subsystem. I have successfully tested the example design using the VCU118 board. In my custom design I added the displayport IP and the necessary IPs just as in the example design. I use the SW code from the example design and i can see that all the initialization happens without any errors. I get the same exact print on the serial termial as the example design. But i do not see the displayport getting detected as an additional screen in my monitor. I have made sure all the connections are same as the example design. The clocks and the resets and the IIC etc. If the connections or the clocks were wrong then initialization would have failed, But it does not. I am running out of ideas here. Anyone have any suggestions on what could be wrong here and any debugging tips?

Unfortunately i wont be able to share the design. 

Regards,

SKa

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skaat27
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Hi @florentw @watari 

Thanks a lot for all the suggestions and help. The issue has been resolved. The problem was with the aux_en pin out that was supposed to be active low. In my design it was active high. Adding an inverter worked. 

 

Regards,

Ska

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watari
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Hi @skaat27 

 

> But i do not see the displayport getting detected as an additional screen in my monitor.

What do you mean ? You use Display Port Rx. How do you output video stream to your monitor ?

 

Also, I'd like to make sure the followings.

 

- Do you implement external retimer (a MegaChips retimer) on your board ?

- Do you prepare suitable EDID on your design ?

- Which link rate did you use or do you want to use ? RBR, HBR, HBR2 or HBR3 ?

- What is target resolution ?

- Can you make sure DPCD register value on your PCB ?

 

Best regards,

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skaat27
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@watari 

Sorry My Bad. Not monitor. I mean laptop. I am using the RX IP. I am new to this displayport interface and not very sure if my responses to your questions will make right sense.

Do you implement external retimer (a MegaChips retimer) on your board ? I am explicity not doing it. I exactly mimiced the example design. Assuming the example design implementents the external retimer. My design should have it too. Is the retimer also called DP159? there are 2 different versions of documentation.

Do you prepare suitable EDID on your design ? Using the same EDID as the example design. Note: The example design works perfectly fine on the same hardware

Which link rate did you use or do you want to use ? Also same configuration as example design Max link rate is 8.1

Can you make sure DPCD register value on your PCB ? Not sure how to do this. Can you explain in detail please

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watari
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Hi @skaat27 

 

>> Do you implement external retimer (a MegaChips retimer) on your board ?

>I am explicity not doing it. I exactly mimiced the example design. Assuming the example design implementents the external retimer. My design should have it too. Is the retimer also called DP159? there are 2 different versions of documentation.

 

No. If your target is HBR3 and/or you use DP 1.4 Rx, you must use MCDP6000 (it's a MegaChips's retimer IC. DP159 is a Texas Instruments's retimer IC for under HBR2.)

If you can share your PCB schematic, it's easy to make sure whether your design is suitable or not...

 

>> Do you prepare suitable EDID on your design ?

>Using the same EDID as the example design. Note: The example design works perfectly fine on the same hardware

 

Is it suitable for your target resolution ?

If no, I suggest you to concern and build EDID value.

 

>>Which link rate did you use or do you want to use ?

>Also same configuration as example design Max link rate is 8.1

 

>>Can you make sure DPCD register value on your PCB ? Not sure how to do this. Can you explain in detail please

 

Can your design output message on serial console ?

Can you use system debugger or DP analyzer ?

 

[Additional question]

Do you use HPD ?

Do you connect HPD between your laptop PC and RP Rx ?

 

Best regards,

skaat27
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@watari 

Thanks for getting back.

Not sure if i can share that but ill try. I have a few doubts. I have the VCU118 eval board. I was able to run the example design for the displayport Rx subsystem 1.4 . If thats works perfectly fine that means the retimer is present in the example design. Am i right? 

attached are the status from my design and example design 

ex-bsp-ex-sw is the example design that works on VCU118

custom-bsp-ex-sw is my design(Basically the same as example design with some additional logic for other stuff not related to displayport)

Edit: Sorry i didn't understand your question before. So to give more idea, we use the inrevium displayport board. This is the one suggested in the Xilinx website. So that has the retimer chip.

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watari
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Hi @skaat27 

 

I guess it's retimer issue.

I can make sure it, if you share your schematic...

 

The reason is below.

 

I guess you use VCU118 and DP 1.4 daughter board (TOKYO ELECTRON DEVICE's inrevium DDisplayPort 1.4 FMC TB-FMCH-VFMC-DP).

This daughter board has MCDP6000 as external clock retimer to remove the random and ISI jitter from source device and the driver software of Xilinx DP 1.4 Rx controls it via IIC@400Hz.

If there is not MCDP6000 on your PCB, DP 1.4 Rx may malfunction. It's relevalant the random and ISI jitter from your laptop PC.

 

Also, not finish to read your log file yet.

But it seems that at least DP Rx IP can't recognize correct resolution. Refer MSA registers.

Maybe it's relevalant MCDP issue.

 

So, I suggest you to make sure the exist of MCDP6000 on your PCB.

 

Best regards,

skaat27
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@watari 

 

Thanks. Check my edit to the previous post. I am using the inrevium card you talk about. That has the MCDP retimer. ALso i2c is set to 400KHz, just as mentioned in the documentation. Let me know when you get a chance to see the logs

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watari
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Hi @skaat27 

 

[log information]

LANE0_1_STATUS (0x043C) in DPCD = 0x0
LANE2_3_STATUS (0x440) in DPCD = 0x0

 

=>

No LANE_x_SYMBOL_LOCKED

No LANE_x_CHANNEL_EQ_DONE

No LANE_x_CLOCK_RECOVERY_DONE

 

According to this log files, clock recovery is failed.

It's principle function.

So, I suspect the followings.

 

- Connection of DP Rx IP (Especially relevalant MCDP6000) in your design

- Clock frequency (rx_lnk_clk, rs_vid_clk, s_axi_aclk/refer PG300 on page 56)

- Reset(mcdp6000_rst/refer PG300 on page 57)

 

https://www.xilinx.com/support/documentation/ip_documentation/v_dp_rxss1/v2_1/pg300-v-dp-rxss1.pdf

 

Would you share block design around DP Rx IP block, if possible ?

 

Best regards,

florentw
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HI @skaat27 and @watari 

I am quite sure there is no need for big debugging. I am quite sure the issue is because @skaat27 forgot to set the VADJ voltage of the VCU118 to 1.8V as recommended in the PG299/PG300:

 

DP.JPG

@watari Thank you for you support


Florent
Product Application Engineer - Xilinx Technical Support EMEA
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skaat27
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@florentw 

Thanks for the suggestion. I didnt read that note. My bad. But in page no.84 of the same documentation it mentions only ZCU102. Should i also do the same for VCU 118? The reason i am confirming this is because the baud rate setting for VCU118 as per documentation was 9600, but it actually is 115200. So wasnt sure if the documentation was outdated or something changed. Also the example design works perfectly fine on VC118. i dont explicitly set the FMC voltage in the example design. Can you please elaborate in detail on how to do this?

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skaat27
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@watari 

I think i might be able to share the block design aroind the DP Rx IP. let me check. Thanks for the suggestion. let me look at clocks.

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skaat27
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@florentw 

So i did download the VCU118 SCUI tool and tried to set the VADJ to 1.8v. Still doesnt work. I am using the example SW and the serial terminal is below.image.png

There are no errors or any messages. The initialization looks right. I checked all the clocks and resets. The connections in my design are exactly same as the example desgn. Any other suggestions please?

 

Thank You

Ska

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skaat27
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Hi @florentw @watari 

Thanks a lot for all the suggestions and help. The issue has been resolved. The problem was with the aux_en pin out that was supposed to be active low. In my design it was active high. Adding an inverter worked. 

 

Regards,

Ska

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skaat27
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Hi,

Looks like got stuck with another issue. I got past the problem of displayport not getting recognized by my laptop. The issue now is that i have ILAs attached to the output of the displayport IP and i see TDATA to be all 0's. To confirm i checked the ILAs on the example design and it looks like TDATA is all 0s in the example design too. 

 

Regards,

Ska

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watari
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Hi @skaat27 

 

Would you share MSA information when you are facing this issue ?

 

Best regards

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skaat27
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Hi @watari 

These are the MSA values. By the way, this is from the Xilinx provided example design for the Rx IP. image.png

This is the ILA trace from the example design. Notice how TDATA is all 0's even though a video source is connected.image.png

 

Regards,

SKa

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watari
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Hi @skaat27 

 

Do you use custom resolution ?

If yes, the route cause is relevant to your desing after DP Rx IP.

So, I suggest you to make sure it.

 

Also, if you want to continue this issue, could you create new thread ?

 

Best regards,

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skaat27
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@watari 

So to be clear, i am running the example design given by Xilinx. This is not my design.

 

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watari
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Hi @skaat27 

 

How do you decide your video timing ?

It's little strange.

Would you share what you want to define video timing ? (horizontal pixel, vertical line, frame rate, pixel clock frequency and so on)

 

Best regards,

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florentw
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HI @skaat27 

Can you create a new topic for this new issue? Else the answer will be burried into this topic and nobody will be able to re-use it ;)

PS. About the doc, I will have it updated (mention VCU118 in Setting the FMC Voltage to 1.8V section and change the UART baud rate)

Thanks


Florent
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skaat27
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