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michelle
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Registered: ‎09-29-2018

DP MST design with streams of different video resolutions

Hi,

I'm using ZCU106 EVM and ran the MST DPTX example based project. The generated DP signal will go to our own DPRX receiver. The current project only supports all MST streams of the same video resolution. I'm modifying to to support different resolution.

I have a question about the pclk provided. My experience working with our receiver is that the pixel clock has to be very accurate based on the timing provided. Previously there's clock wizard which is dynamically programmed to provide the pixel clock to all streams. Now, I created a 2nd clock wizard and programmed it to have the pixel clock for the 2nd stream. I've modified the driver to support different resolution for 2nd stream, but I'm still having trouble getting 2nd stream up. I wonder if Xilinx experts can share some insight on how to set up the clock system.

Thanks and Regards,

Michelle

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florentw
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Registered: ‎11-09-2015

Hi @michelle 

I am not sure if your question is related to the TX or RX side? I assume you are talking about the RX side correct?

The way to set the clocking on the RX for MST is basically the same as per SST. You read the MSA values corresponding to this specific stream and then you use this MSA values to program the MMCM accordingly.

I can see that the registers for the MSA values for the MST streams are missing in the PG300. You can have the correct addresses in the drivers (I just reported this to the dev team to have the PG updated):

https://github.com/Xilinx/embeddedsw/blob/f975a0ea90930587ab55e4d920a31950bd373fa8/XilinxProcessorIPLib/drivers/dp14/src/xdp_hw.h#L1265

For example, MSA of stream 2 start in reg 0x540 

Is that the information you were looking for?


Florent
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michelle
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Registered: ‎09-29-2018

@florentw 

Sorry I wasn't being clear on my question.

The question is about DPTX design. The current DPTX MST project has all streams pixel clock the same. I'm now working on MST with two streams of different resolution so I provided different clock wizard to the streams. I wonder if you expect any issue with such change.

 

Thanks and Regards,

Michelle

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florentw
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Hi @michelle 

For TX you know what resolutions you are sending so you can just set the clocking wizard accordingly. I am not sure exactly what you are looking for? If the clocks are correct for each stream then I am not expecting any issue

Are you using Native interface or AXI4-Streams?


Florent
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michelle
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@florentw ,

Thanks for the confirmation.

I'm using AXI4 stream format.

 

Thanks and Regards,

Michelle

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florentw
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HI @michelle 

Do you have any update on this?


Florent
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michelle
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Hi @florentw 

I just got to use QD box to verify the design today. Unfortunately, it does not work in the asymmetric MST mode. (asymmetric means two streams of different resolution).

If I program each stream of the same resolution, I can see output. If they are programmed of different resolution, none of the stream came out. 

I took snapshot of the input streams to DP IP block, also the clock connection on the block diagram. clock wiz 0 is for first stream and clock wiz 1 is for 2nd stream.

The ILA capture is for first stream 1080p and 2nd stream 720p.

Could you help take a look? Thanks!
Regards,

Michelleclk_wiz0clk_wiz0clk_wiz 1clk_wiz 11080p1080p720p720p

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florentw
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Registered: ‎11-09-2015

HI @michelle 

What do you have on the receiver side? Is the training succeed? Can you read the correct MSA values for each stream? Do you have any debug information on it?


Florent
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michelle
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@florentw ,

The link is locked. The MSA of the first stream can be read correctly. The second stream MSA is all zero.

Thanks and Regards,

Michelle

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florentw
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HI @michelle 

The it might be the issue. Are you setting the MSA values correctly for the second stream? Can you share a register dump for the DP TX core?


Florent
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michelle
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@florentw 

Correction of the result with latest test.  I was able to get the first stream out correctly. Only the 2nd stream is not working. The MSA of the 2nd stream is not detected. I will generate the register dump and send later.

Thanks and Regards,

Michelle

 

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michelle
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@florentw 

Please see the snapshot of the MSA of streams. I assigned 720p and 1080p to 1st and 2nd stream respectively.

MSA.png

Regards,

Michelle

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florentw
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HI @michelle 

Could you grap a register dump of the core using xsct to read into it? Looking only at the structure variable does not tell if the settings were applied.


Florent
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michelle
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Hi @florentw ,

I'm not sure how to use xsct to get core register directly, but I was able to use xsct mrd command to read the DP IP reg using its address. It's the same as I got from memory browser. 

In momory map, the DP IP base address is 0xA0100000.  

As you can see, the main stream attribute starts at offset of 0x180. 2nd stream attributes starts at 0x500. 

I checked the values and they are consistent with the video format I selected: 1080p for 1st stream and 720p for 2nd stream. 

Address 0 - 3 4 - 7 8 - B C - F

00000000A0100000 0000001E 00000004 00000001 00000000

00000000A0100180 00000898 00000465 00000003 0000002C
00000000A0100190 00000005 00000780 00000438 000000C0
00000000A01001A0 00000029 00000020 00000000 00001779
00000000A01001B0 00000008 00008000 00000001 00000B3C
00000000A01001C0 00000000 00000008 00000300 00000000
00000000A01001D0 000802EE 00040177 00000000 00000000
00000000A01001E0 00000000 00000000 00000000 00000000

00000000A0100500 00000672 000002EE 00000003 00000028
00000000A0100510 00000005 00000500 000002D0 00000104
00000000A0100520 00000019 00000020 00000000 0001220A
00000000A0100530 00000004 00008000 00000001 0000077C
00000000A0100540 00000000 00000004 00000180 00000000

More register values are in attached file. 

Does that mean the programming of DP core is correct? If you need me to run xsct dump, could you send an example code so I can exactly what to do?

Thanks and Regards,

Michelle

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florentw
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HI @michelle 

Yes the programming of the DP core seems correct. I am not sure why the sink is not detecting the MSA values for the second stream.

Can you check the full steps to enable MST?

MST.PNG

 

Florent
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michelle
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@florentw 

I agree the issue is that the 2nd stream parameters are not seemed to be used. Only when the two streams are of the same resolution, the outputs are okay. It seems that only main stream parameters are used.

We couldn't exactly follow the steps you listed.

Step 3: If this is enabled, we have issue do link training. Therefore I have been setting 0xD0 to value 0x0 instead of 0x1. 

Step 5a: I can see the step program VC payload. During debug, I can step through it and it's writing to the register with VcId value. Here's the code in xdp_mst.c:  for (Index = StartTs; Index < (StartTs + Ts); Index++) {
XDp_WriteReg(InstancePtr->Config.BaseAddr,
(XDP_TX_VC_PAYLOAD_BUFFER_ADDR + (4 * Index)), VcId);
}

However, the readout of register 0x800 and above are all zero. You can also see those in the dump file previously provided.

Are you are aware any issue associated with above steps? 

Thanks!

Regards,

Michelle

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florentw
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HI @michelle 

No I am not aware of any issue with the above steps.

You are saying that the training is failing when MST is enabled before the training. I assume your QD analyzer can generate a AUX log? Could you share it in HTML format?

Thanks


Florent
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michelle
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@florentw ,

I first need to clarify my previous statement. We have QD box and also our own DPRX receiver. I had a confusion when I mentioned about the failed link training and having to turn off MST enable. That issue only shows up only in our own DPRX case.

As to QD box, no training issue. I re-worked on SDK project and make sure the suggested MST procedures are followed and captured the AUX transaction. In this case, I send 1080p and 720p 2xMST streams and the link training is successful. The first stream is good, no 2nd stream. Please see attached htm.

Is there any asymmtric project Xilinx can share as an example? It is important for us to make asymmetric case working. Thanks!

Regards,

Michelle

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florentw
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Hi @michelle 

Then if the training is successful, there is not much I can get from the AUX log.

The TX only and the pass-through should be able to do asymmetric. I have already tried it with multiple monitor connected in daisy chain with different resolutions.

Maybe try to check if you have monitor you could try in daisy chain (first with a GPU, then with the PT design, then with the TX only)

 


Florent
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michelle
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Hi @florentw ,

I modified mst example project using 2020.1 version and got asymmetric mst working.

Thanks and Regards,

Michelle

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michelle
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@florentw 

One issue with the MST design is that it turns out both streams are still sharing the same pixel clock. I was able to get 1080p and 720p streams out but 1080p is only 30fps and pixel clock is 74.22MHz. The ideal solution is to have streams each has individual pixel clock. I'll give it a try and let you know how it goes.

Thanks!

Regards,

Michelle