07-26-2021 10:48 AM
I am working on a DP 1.4 TX only custom setup using a Zynq UltraScale+ device and using Vivado/Vitis 2020.1.
I am having application problems where code portions of my DDR is being overwritten, and it appears to be due to the XPAR_TX_V_DP_TXSS1_0_TIMER_BASEADDR being set to 0x00008000.
The problem occurs when the DP TXSS timer initialization is set which overwrites the code I have at DDR address 0x8000.
Can somebody from Xilinx please confirm if this is a bug, and how I can fix it?
Vivado Memory Addresses:
Xparameters.h showing addresses:
07-26-2021 12:45 PM
This is the function call that ends up overwriting my code.
This XTmrCtr_Initialize function should work fine for the non-DP timers since they use an absolute address, but the DP TX Timer seems to use a relative address for the BaseAddress.
07-26-2021 01:02 PM - edited 07-26-2021 01:02 PM
I do notice that this DP TX TIMER BASEADDR does not show up in xparameters.h until HDCP 1.3 is added to the DP 1.4 TX IP block in Vivado.
07-26-2021 01:38 PM
I think this portion of the dp14txss_v6_3 xdptxss.c XDpTxSs_CfgInitialize function needs to be rewritten somehow since the XTmrCtr_Intialize function uses absolute Config BaseAddress values.
I attempted to take the guts of XTmrCtr_Initialize and add in the DP TX BaseAddress to the timer BaseAddress offset as shown below and use this updated code in the dp14txss_v6_3/xdptxss.c XDpTxSs_CfgInitialize function.
I had this XTmrCtrConfigPtr definition at the top of the XDpTxSs_CfgInitialize function.
The changes shown above seemed to have fixed my memory-being-overwritten problem.
Once Xilinx confirms the issue and my fix is valid I will mark this as resolved.