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Adventurer
Adventurer
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Registered: ‎10-02-2014

DPHY 4.1 placement violation

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.Hello We ported a design from Vivado 2016 with D-PHY 3.0 to Vivado 2019 With D-PHY 4.1

The device is a zynq xc7z20-clg484, there are two dphuy cores each driving 4 lanes, a master with the MCM inside and a slave.

In VIvado 2016 the design fits and runs, when ported to 2019.2 it fails with a placement error.

this is the log of placer:

Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device
ERROR: [Place 30-149] Unroutable Placement! A MMCM / (BUFIO/BUFR) component pair is not placed in a routable site pair. The MMCM component can use the dedicated path between the MMCM and the (BUFIO/BUFR) if both are placed in the same clock region or if they are placed in horizontally adjacent clock regions. If this sub optimal condition is acceptable for this design, you may use the CLOCK_DEDICATED_ROUTE constraint in the .xdc file to demote this message to a WARNING. However, the use of this override is highly discouraged. These examples can be used directly in the .xdc file to override this clock rule.
< set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets CustomLogic_INST/comp_Dual_DSI2_transmitter/mipi_dphy_master/inst/inst/mipi_dphy_0_1_tx_support_i/master_tx.mipi_dphy_0_1_tx_clock_module_support_i/mipi_dphy_0_1_clock_module_tx_i/inst/mmcm_clk_out0] >

CustomLogic_INST/comp_Dual_DSI2_transmitter/mipi_dphy_master/inst/inst/mipi_dphy_0_1_tx_support_i/master_tx.mipi_dphy_0_1_tx_clock_module_support_i/mipi_dphy_0_1_clock_module_tx_i/inst/mmcm_adv_inst (MMCME2_ADV.CLKOUT0) is provisionally placed by clockplacer on MMCME2_ADV_X1Y1
CustomLogic_INST/comp_Dual_DSI2_transmitter/mipi_dphy_master/inst/inst/mipi_dphy_0_1_tx_support_i/master_tx.mipi_dphy_0_1_tx_clock_module_support_i/clk_fwd_bufio_i (BUFIO.I) is provisionally placed by clockplacer on BUFIO_X1Y1
CustomLogic_INST/comp_Dual_DSI2_transmitter/mipi_dphy_master/inst/inst/mipi_dphy_0_1_tx_support_i/master_tx.mipi_dphy_0_1_tx_clock_module_support_i/div_clk_gen (BUFR.I) is provisionally placed by clockplacer on BUFR_X1Y1

The above error could possibly be related to other connected instances. Following is a list of
all the related clock rules and their respective instances.

Clock Rule: rule_mmcm_bufg
Status: PASS
Rule Description: An MMCM driving a BUFG must be placed on the same half side (top/bottom) of the device
CustomLogic_INST/PixelClkPLL_Inst/inst/mmcm_adv_inst (MMCME2_ADV.CLKFBOUT) is provisionally placed by clockplacer on MMCME2_ADV_X1Y0
CustomLogic_INST/PixelClkPLL_Inst/inst/clkf_buf (BUFG.I) is provisionally placed by clockplacer on BUFGCTRL_X0Y0

Clock Rule: rule_bufh_bufr_ramb
Status: PASS
Rule Description: Reginal buffers in the same clock region must drive a total number of brams less
than the capacity of the region
CustomLogic_INST/comp_Dual_DSI2_transmitter/mipi_dphy_master/inst/inst/mipi_dphy_0_1_tx_support_i/master_tx.mipi_dphy_0_1_tx_clock_module_support_i/div_clk90_gen (BUFR.O) is provisionally placed by clockplacer on BUFR_X1Y0

Clock Rule: rule_bufr_IoClkLds
Status: PASS
Rule Description: A BUFR driving any number of IOBs must be placed within the same clock region
CustomLogic_INST/comp_Dual_DSI2_transmitter/mipi_dphy_master/inst/inst/mipi_dphy_0_1_tx_support_i/master_tx.mipi_dphy_0_1_tx_clock_module_support_i/div_clk90_gen (BUFR.O) is provisionally placed by clockplacer on BUFR_X1Y0
CustomLogic_INST/comp_Dual_DSI2_transmitter/mipi_dphy_master/inst/inst/mipi_dphy_0_1_tx_support_i/master_tx.mipi_dphy_0_1_tx_ioi_i/dl0_oserdese2_master (OSERDESE2.CLKDIV) is locked to OLOGIC_X1Y20
CustomLogic_INST/comp_Dual_DSI2_transmitter/mipi_dphy_master/inst/inst/mipi_dphy_0_1_tx_support_i/master_tx.mipi_dphy_0_1_tx_ioi_i/dl1_obufds_inst.dl1_oserdese2_master (OSERDESE2.CLKDIV) is locked to OLOGIC_X1Y18
CustomLogic_INST/comp_Dual_DSI2_transmitter/mipi_dphy_master/inst/inst/mipi_dphy_0_1_tx_support_i/master_tx.mipi_dphy_0_1_tx_ioi_i/dl2_obufds_inst.dl2_oserdese2_master (OSERDESE2.CLKDIV) is locked to OLOGIC_X1Y16
CustomLogic_INST/comp_Dual_DSI2_transmitter/mipi_dphy_master/inst/inst/mipi_dphy_0_1_tx_support_i/master_tx.mipi_dphy_0_1_tx_ioi_i/dl3_obufds_inst.dl3_oserdese2_master (OSERDESE2.CLKDIV) is locked to OLOGIC_X1Y14
CustomLogic_INST/comp_Dual_DSI2_transmitter/mipi_dphy_slave/inst/inst/master_tx.mipi_dphy_0_2_tx_ioi_i/dl0_oserdese2_master (OSERDESE2.CLKDIV) is locked to OLOGIC_X1Y10
CustomLogic_INST/comp_Dual_DSI2_transmitter/mipi_dphy_slave/inst/inst/master_tx.mipi_dphy_0_2_tx_ioi_i/dl1_obufds_inst.dl1_oserdese2_master (OSERDESE2.CLKDIV) is locked to OLOGIC_X1Y8
CustomLogic_INST/comp_Dual_DSI2_transmitter/mipi_dphy_slave/inst/inst/master_tx.mipi_dphy_0_2_tx_ioi_i/dl2_obufds_inst.dl2_oserdese2_master (OSERDESE2.CLKDIV) is locked to OLOGIC_X1Y6
CustomLogic_INST/comp_Dual_DSI2_transmitter/mipi_dphy_slave/inst/inst/master_tx.mipi_dphy_0_2_tx_ioi_i/dl3_obufds_inst.dl3_oserdese2_master (OSERDESE2.CLKDIV) is locked to OLOGIC_X1Y4

Clock Rule: rule_bufr_mmcm
Status: PASS
Rule Description: A BUFR driving an MMCM must be placed within the same clock region
CustomLogic_INST/comp_Dual_DSI2_transmitter/mipi_dphy_master/inst/inst/mipi_dphy_0_1_tx_support_i/master_tx.mipi_dphy_0_1_tx_clock_module_support_i/div_clk90_gen (BUFR.O) is provisionally placed by clockplacer on BUFR_X1Y0
CustomLogic_INST/PixelClkPLL_Inst/inst/mmcm_adv_inst (MMCME2_ADV.CLKIN1) is provisionally placed by clockplacer on MMCME2_ADV_X1Y0

Clock Rule: rule_mmcm_bufg
Status: PASS
Rule Description: An MMCM driving a BUFG must be placed on the same half side (top/bottom) of the device
CustomLogic_INST/comp_Dual_DSI2_transmitter/mipi_dphy_master/inst/inst/mipi_dphy_0_1_tx_support_i/master_tx.mipi_dphy_0_1_tx_clock_module_support_i/mipi_dphy_0_1_clock_module_tx_i/inst/mmcm_adv_inst (MMCME2_ADV.CLKFBOUT) is provisionally placed by clockplacer on MMCME2_ADV_X1Y1
CustomLogic_INST/comp_Dual_DSI2_transmitter/mipi_dphy_master/inst/inst/mipi_dphy_0_1_tx_support_i/master_tx.mipi_dphy_0_1_tx_clock_module_support_i/clkfb_bufg (BUFG.I) is provisionally placed by clockplacer on BUFGCTRL_X0Y30

Clock Rule: rule_mmcm_bufr_bufio
Status: FAIL
Rule Description: An MMCM driving a BUFR/BUFIO must both be in the same clock region
CustomLogic_INST/comp_Dual_DSI2_transmitter/mipi_dphy_master/inst/inst/mipi_dphy_0_1_tx_support_i/master_tx.mipi_dphy_0_1_tx_clock_module_support_i/mipi_dphy_0_1_clock_module_tx_i/inst/mmcm_adv_inst (MMCME2_ADV.CLKOUT1) is provisionally placed by clockplacer on MMCME2_ADV_X1Y1
CustomLogic_INST/comp_Dual_DSI2_transmitter/mipi_dphy_master/inst/inst/mipi_dphy_0_1_tx_support_i/master_tx.mipi_dphy_0_1_tx_clock_module_support_i/data_fwd_bufio_i (BUFIO.I) is provisionally placed by clockplacer on BUFIO_X1Y0
CustomLogic_INST/comp_Dual_DSI2_transmitter/mipi_dphy_master/inst/inst/mipi_dphy_0_1_tx_support_i/master_tx.mipi_dphy_0_1_tx_clock_module_support_i/div_clk90_gen (BUFR.I) is provisionally placed by clockplacer on BUFR_X1Y0
ERROR: The above is also an illegal clock rule
Workaround: < set_property CLOCK_DEDICATED_ROUTE ANY_CMT_COLUMN [get_nets CustomLogic_INST/comp_Dual_DSI2_transmitter/mipi_dphy_master/inst/inst/mipi_dphy_0_1_tx_support_i/master_tx.mipi_dphy_0_1_tx_clock_module_support_i/mipi_dphy_0_1_clock_module_tx_i/inst/mmcm_clk_out1] >

Clock Rule: rule_bufio_clklds
Status: PASS
Rule Description: A BUFIO driving any number of IOBs must be placed within the same bank. In V7, there
is at most one IO bank in each clock region so the SameClockRegion rule is sufficient to satisfy the
requirement.
CustomLogic_INST/comp_Dual_DSI2_transmitter/mipi_dphy_master/inst/inst/mipi_dphy_0_1_tx_support_i/master_tx.mipi_dphy_0_1_tx_clock_module_support_i/clk_fwd_bufio_i (BUFIO.O) is provisionally placed by clockplacer on BUFIO_X1Y1
CustomLogic_INST/comp_Dual_DSI2_transmitter/mipi_dphy_master/inst/inst/mipi_dphy_0_1_tx_support_i/master_tx.mipi_dphy_0_1_tx_ioi_i/clk_fwd (OSERDESE2.CLK) is locked to OLOGIC_X1Y12
CustomLogic_INST/comp_Dual_DSI2_transmitter/mipi_dphy_slave/inst/inst/master_tx.mipi_dphy_0_2_tx_ioi_i/clk_fwd (OSERDESE2.CLK) is locked to OLOGIC_X1Y2

Clock Rule: rule_bufh_bufr_ramb
Status: PASS
Rule Description: Reginal buffers in the same clock region must drive a total number of brams less
than the capacity of the region
CustomLogic_INST/comp_Dual_DSI2_transmitter/mipi_dphy_master/inst/inst/mipi_dphy_0_1_tx_support_i/master_tx.mipi_dphy_0_1_tx_clock_module_support_i/div_clk_gen (BUFR.O) is provisionally placed by clockplacer on BUFR_X1Y1

Clock Rule: rule_bufr_IoClkLds
Status: PASS
Rule Description: A BUFR driving any number of IOBs must be placed within the same clock region
CustomLogic_INST/comp_Dual_DSI2_transmitter/mipi_dphy_master/inst/inst/mipi_dphy_0_1_tx_support_i/master_tx.mipi_dphy_0_1_tx_clock_module_support_i/div_clk_gen (BUFR.O) is provisionally placed by clockplacer on BUFR_X1Y1
CustomLogic_INST/comp_Dual_DSI2_transmitter/mipi_dphy_master/inst/inst/mipi_dphy_0_1_tx_support_i/master_tx.mipi_dphy_0_1_tx_ioi_i/clk_fwd (OSERDESE2.CLKDIV) is locked to OLOGIC_X1Y12
CustomLogic_INST/comp_Dual_DSI2_transmitter/mipi_dphy_slave/inst/inst/master_tx.mipi_dphy_0_2_tx_ioi_i/clk_fwd (OSERDESE2.CLKDIV) is locked to OLOGIC_X1Y2

Clock Rule: rule_bufio_clklds
Status: PASS
Rule Description: A BUFIO driving any number of IOBs must be placed within the same bank. In V7, there
is at most one IO bank in each clock region so the SameClockRegion rule is sufficient to satisfy the
requirement.
CustomLogic_INST/comp_Dual_DSI2_transmitter/mipi_dphy_master/inst/inst/mipi_dphy_0_1_tx_support_i/master_tx.mipi_dphy_0_1_tx_clock_module_support_i/data_fwd_bufio_i (BUFIO.O) is provisionally placed by clockplacer on BUFIO_X1Y0
CustomLogic_INST/comp_Dual_DSI2_transmitter/mipi_dphy_master/inst/inst/mipi_dphy_0_1_tx_support_i/master_tx.mipi_dphy_0_1_tx_ioi_i/dl0_oserdese2_master (OSERDESE2.CLK) is locked to OLOGIC_X1Y20
CustomLogic_INST/comp_Dual_DSI2_transmitter/mipi_dphy_master/inst/inst/mipi_dphy_0_1_tx_support_i/master_tx.mipi_dphy_0_1_tx_ioi_i/dl1_obufds_inst.dl1_oserdese2_master (OSERDESE2.CLK) is locked to OLOGIC_X1Y18
CustomLogic_INST/comp_Dual_DSI2_transmitter/mipi_dphy_master/inst/inst/mipi_dphy_0_1_tx_support_i/master_tx.mipi_dphy_0_1_tx_ioi_i/dl2_obufds_inst.dl2_oserdese2_master (OSERDESE2.CLK) is locked to OLOGIC_X1Y16
CustomLogic_INST/comp_Dual_DSI2_transmitter/mipi_dphy_master/inst/inst/mipi_dphy_0_1_tx_support_i/master_tx.mipi_dphy_0_1_tx_ioi_i/dl3_obufds_inst.dl3_oserdese2_master (OSERDESE2.CLK) is locked to OLOGIC_X1Y14
CustomLogic_INST/comp_Dual_DSI2_transmitter/mipi_dphy_slave/inst/inst/master_tx.mipi_dphy_0_2_tx_ioi_i/dl0_oserdese2_master (OSERDESE2.CLK) is locked to OLOGIC_X1Y10
CustomLogic_INST/comp_Dual_DSI2_transmitter/mipi_dphy_slave/inst/inst/master_tx.mipi_dphy_0_2_tx_ioi_i/dl1_obufds_inst.dl1_oserdese2_master (OSERDESE2.CLK) is locked to OLOGIC_X1Y8
CustomLogic_INST/comp_Dual_DSI2_transmitter/mipi_dphy_slave/inst/inst/master_tx.mipi_dphy_0_2_tx_ioi_i/dl2_obufds_inst.dl2_oserdese2_master (OSERDESE2.CLK) is locked to OLOGIC_X1Y6
CustomLogic_INST/comp_Dual_DSI2_transmitter/mipi_dphy_slave/inst/inst/master_tx.mipi_dphy_0_2_tx_ioi_i/dl3_obufds_inst.dl3_oserdese2_master (OSERDESE2.CLK) is locked to OLOGIC_X1Y4

This is the pinout:

set_property PACKAGE_PIN U16 [get_ports TX0_D0n]
set_property PACKAGE_PIN U15 [get_ports TX0_D0p]
set_property PACKAGE_PIN V17 [get_ports TX0_D1n]
set_property PACKAGE_PIN U17 [get_ports TX0_D1p]
set_property PACKAGE_PIN AB17 [get_ports TX0_D2n]
set_property PACKAGE_PIN AA17 [get_ports TX0_D2p]
set_property PACKAGE_PIN AB16 [get_ports TX0_D3n]
set_property PACKAGE_PIN AA16 [get_ports TX0_D3p]
set_property PACKAGE_PIN V15 [get_ports TX0_CLKn]
set_property PACKAGE_PIN V14 [get_ports TX0_CLKp]
set_property PACKAGE_PIN W13 [get_ports TX1_D0n]
set_property PACKAGE_PIN V13 [get_ports TX1_D0p]
set_property PACKAGE_PIN Y15 [get_ports TX1_D1n]
set_property PACKAGE_PIN W15 [get_ports TX1_D1p]
set_property PACKAGE_PIN AA14 [get_ports TX1_D2n]
set_property PACKAGE_PIN Y14 [get_ports TX1_D2p]
set_property PACKAGE_PIN AA13 [get_ports TX1_D3n]
set_property PACKAGE_PIN Y13 [get_ports TX1_D3p]
set_property PACKAGE_PIN AB14 [get_ports TX1_CLKp]
set_property PACKAGE_PIN AB15 [get_ports TX1_CLKn]

What's wrong?

 

 

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Adventurer
Adventurer
168 Views
Registered: ‎10-02-2014

Hello Leo, the IPs were already set like this, the problem was due to another PLL that was interfering with the placement, strange that 2016 managed to fit without problems.

Thanks for your support,

Marco

 

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Xilinx Employee
Xilinx Employee
182 Views
Registered: ‎03-30-2016

Hello @marcoventurini 

An mentioned in this resources utilization page:
   https://www.xilinx.com/support/documentation/ip_documentation/ru/mipi-dphy.html
Current MIPI D-PHY TX with shared logic in the core is using 1 MMCM and 1 BUFR,

Since there is only one MMCM in each CMT,
  7SERIES_1MMCM_per_CMT.jpg

You might need to set one of your MIPI D-PHY TX IPs with "Shared logic in example design" and connect those IPs as follow :
MIPI_DPHY_TX_master_slave_clock_sharing.jpg

Please let me know if you still have difficulty implementing your design.

Thanks & regards
Leo

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Adventurer
Adventurer
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Registered: ‎10-02-2014

Hello Leo, the IPs were already set like this, the problem was due to another PLL that was interfering with the placement, strange that 2016 managed to fit without problems.

Thanks for your support,

Marco

 

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Xilinx Employee
Xilinx Employee
148 Views
Registered: ‎03-07-2018

Hello @marcoventurini 

Xilinx MIPI DPHY IP v4.1 is not supported By Vivado 2016. For more details please check https://www.xilinx.com/support/answers/54550.html

I am interested to know, how you managed to perform placement and routing of your design in Vivado 2016. 

Please note updated versions of Vivado comes with bug fixes, improvements and updates. 

So, kindly confirm your system is working well on hardware or not, so others can be benefited whoever come across this post. 

Regards,
Bhushan

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Adventurer
Adventurer
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Registered: ‎10-02-2014

Actually the problem was highlighted only in the 2019 version.

The PLL was incorrectly set to take the input clock from an input pin while it was coming from an internal global buffer (the MIPI phy byte clock).

It may just be that the 2016 version was tolerant to this misconfgiuration.

Marco