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Visitor
Visitor
257 Views
Registered: ‎08-08-2019

DPHY not response to the phystopstate signal

Hi

I instantiated a mipi dphy IP in xczu4eg-fbvb900-1-e device and using it to test display scenario. But we met some issues.
When dsi_controller send the request to dphy, dphy can’t response the correct phystopstate to dsi_controller.
You can see the exception of the interactive signal in the screenshot below.The configuration of mipi dphy is also show below.

 When dsi_controller send request to dphy(data-lane0/1/2/3),  which condition does dphy need to  meet to ensure the correct inversion of phystopstate signal?

 
 

 

snapshop of wave.png
dphy configuration.png
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Xilinx Employee
Xilinx Employee
241 Views
Registered: ‎03-30-2016

Hello @zhxwu 

I can see that you are using MIPI D-PHY TX in US+ device.

1. Are you still using Vivado 2018.2 ? ( or have you migrate to a newer Vivado version ? )

2. Do you use Xilinx MIPI DSI TX Subsystem IP ?
    # If yes could you please share the GUI screenshot ?

3. Could you please probe the following signal using ILA ?
cl_enable
cl_stopstate
cl_txrequesths
dl*_enable
dl*_stopstate
dl*_txreadyhs
dl*_txrequesths
mmcm_lock_out
init_done

4. Is the 200MHz clock running and stable ?

5. Could you please check that INIT_DONE=1 and mmcm_lock_out=1 before asserting any cl_txrequesths/dl*_txrequesths signals ?

6. Could you please try to enable dl*_txrequesths at the same time (0-->1) ? I do not see any value for giving control like this )
MIPI_FORUM_waveform.png
7. I can see that stopstate for data lane1 is always "0" ? Do you know why this happens ?
( I am suspected INIT_DONE is not asserted yet )

Regards
Leo

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Xilinx Employee
Xilinx Employee
86 Views
Registered: ‎03-30-2016

Hello @zhxwu 

Do you have any update on this ?
Is this issue solved already ?

Thanks & regards
Leo

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