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Observer
Observer
7,763 Views
Registered: ‎10-30-2007

Digital Down Converter error

Hi all, can anyone help me with the error i encountered in using system geberator to create a DDC for GSM signals? I have attached the design.
Seems like it keep generating an error that says an illegal period has been set for the system in the DDS portion of my DDC design
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Xilinx Employee
Xilinx Employee
7,753 Views
Registered: ‎08-07-2007

Please open a WebCase with Xilinx Technical Support for help with a specific model issue such as this.
http://support.xilinx.com/support/clearexpress/websupport.htm
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