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sdcf2003
Observer
Observer
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Registered: ‎05-16-2018

Directly connect video-in-axi4-stream with axi4-stream- to-video-out without VDMA

I built a video stream line:adv7611->video-in-axi4-stream->axi4-stream- to-video-out->adv7511 with zedboard+avnet FMC module. I didn't insert a VDMA between Video-In-AXI4-Stream and AXI4-Stream-to-Video-out like reference design.

   I found that the locked signal of AXI4-Stream-to-Video-out always kept low. It means that the AXI4-Stream-to-Video-out didn't locked the input axi4-stream video.

  The video-in-axi4-stream and axi4-stream- to-video-out share same aclk(150M) and reset signal. The output of adv7611 is 1080p60hz yuv4:2:2. The axi4-stream- to-video-out works in slave mode. Video timing controller is 1080p.

Following is the block design diagram.

无标题.png

But if replaced the Video-to AXI4-Stream and ADV7611 with a Test Pattern Generator. I can get a GOOD output of ADV7511 and a high level locked signal.

So I wonder what the differences between a real video and Test Pattern Generator?

There must be something out of sync.  In this case how to configure these IP? 

The VDMA is necessary?

I add a system ila between  Video-to AXI4-Stream and AXI4-Stream-to-Video-out.

I got following ila capture image. The EOL(TLAST) and EOF(TUSR)  signals look like good.

adv7611_adv7511_3.png

Following is the status signal of AXI4-Stream-to-Video-out.

The status is 0x000c008f

adv7611_adv7511_4.png

 

 

 

 

 

 

 

 

 

 

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3 Replies
watari
Teacher
Teacher
235 Views
Registered: ‎06-16-2013

Hi @sdcf2003 

 

>So I wonder what the differences between a real video and Test Pattern Generator?

 

The differences between them are video format (NV16 vs guess RGB888) and internal video timing.

 

>There must be something out of sync. In this case how to configure these IP?

 

You must consider to use remapper or to change video format.

 

>The VDMA is necessary?

 

It depends on what you want to achieve.

 

Best regards,

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florentw
Moderator
Moderator
201 Views
Registered: ‎11-09-2015

Hi @sdcf2003 

First you might want to read my article on how to debug the AXI4-Stream to video out:

Video Beginner Series 8: Debugging the AXI4-Stream to Video Out IP

But here the issue seems pretty clear. We can see that the AXI4-Stream to video out is always in underflow. So it means that there is not enough data coming in.

The difference with the TPG is that it does not have blanking period so it can feed the data during this periods.

An AXI VDMA can definitely help here. But it should be possible without it.

You might want to read the section Buffer requirements of the PG044. So with that you might see that increasing the hysteresis level of the AXI4-Stream to video out might help.

There are other options to explore (using the VTC as detector + generator to have a fsync) which can help


Florent
Product Application Engineer - Xilinx Technical Support EMEA
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florentw
Moderator
Moderator
126 Views
Registered: ‎11-09-2015

HI @sdcf2003 

Any update on this? Were you able to make your project working?


Florent
Product Application Engineer - Xilinx Technical Support EMEA
**~ Don't forget to reply, give kudos, and accept as solution.~**
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