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Registered: ‎03-14-2019

DisplayPort 1.4 RX and TX subsystem training failed when connect to each other

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Hi,

I am trying to implement DisplayPort 1.4 RX-only and TX-only on my custom board with a Ultrascale+ soc. Instead using MCDP6000 for RX and DP141 for TX, we use DP142 redriver for both the RX and TX ports on the board. I built the RX/TX system base on the RX-only and TX-only example designs, and the RX-only project works fine with graphics cards and the TX-only normally completes the link training and successfully outputs videos to the testing monitors.

But the problem is , a board with RX-only can't work with another board with TX-only. The log shows the link training is done when two boards are connected, then the RX will accumulate the DpRxSsInst.VBlankCount. But the VerticalBlank interrupt doesn't show up continuously, VerticalBlank interrupt and NoVideo interrupt alternate and finally the training failed. Is the problem on the pattern generator in TX? But the TX works fine with monitors.

Any help will be appreciated.

Thanks,

Bill

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Moderator
Moderator
357 Views
Registered: ‎10-04-2017

Hi 904860365@qq.com Bill,

I am not 100% if you have 2 boards or 1, but I will reply based on you having 1 board with an RX interface and a TX interface.

I am also assuming that these designs RX and TX are running on the same MP.
Please correct me if either of these assumptions is incorrect.

Moving forward:

Test 1. TX -> Monitor : Confirmed working

Test 2. Source -> RX : Confirmed working

Please run Test 3. Both Test 1 and Test 2 at the same time. This will verify both your HW and SW working correctly when connected to known working links.


If Test 3 fails, you will need to figure out if there is an HW(PCB level) or SW(Application level) issue that is causing the problem. 
If Test 3 works, you know that there is only an issue in loopback (TX->RX).

In this case, do you have access to an AUX analyzer? If so, this will tell you exactly what the issue is. It could be that your DP141 is not configured correctly or that there is a problem with the driver.


If you do not have an AUX analyzer, you can start making educated guesses. You can compare the PHY and RX/TX logs in the working case vs the non working case.  **It seems that you have done a little bit of this by looking at the ISRs.

The next step is to check if the ISR is not being registered properly by the MP or if there is an issue receiving the Vertical Blank interrupt over the link.
When you are doing this debugging, the status registers of the PHY and DP core will be a good guide.

-Sam

 

 

Don't forget to reply, kudo, and accept as solution.

Xilinx Video Design Hub

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4 Replies
Moderator
Moderator
358 Views
Registered: ‎10-04-2017

Hi 904860365@qq.com Bill,

I am not 100% if you have 2 boards or 1, but I will reply based on you having 1 board with an RX interface and a TX interface.

I am also assuming that these designs RX and TX are running on the same MP.
Please correct me if either of these assumptions is incorrect.

Moving forward:

Test 1. TX -> Monitor : Confirmed working

Test 2. Source -> RX : Confirmed working

Please run Test 3. Both Test 1 and Test 2 at the same time. This will verify both your HW and SW working correctly when connected to known working links.


If Test 3 fails, you will need to figure out if there is an HW(PCB level) or SW(Application level) issue that is causing the problem. 
If Test 3 works, you know that there is only an issue in loopback (TX->RX).

In this case, do you have access to an AUX analyzer? If so, this will tell you exactly what the issue is. It could be that your DP141 is not configured correctly or that there is a problem with the driver.


If you do not have an AUX analyzer, you can start making educated guesses. You can compare the PHY and RX/TX logs in the working case vs the non working case.  **It seems that you have done a little bit of this by looking at the ISRs.

The next step is to check if the ISR is not being registered properly by the MP or if there is an issue receiving the Vertical Blank interrupt over the link.
When you are doing this debugging, the status registers of the PHY and DP core will be a good guide.

-Sam

 

 

Don't forget to reply, kudo, and accept as solution.

Xilinx Video Design Hub

View solution in original post

Moderator
Moderator
334 Views
Registered: ‎11-09-2015

904860365@qq.com wrote:

Hi,

I am trying to implement DisplayPort 1.4 RX-only and TX-only on my custom board with a Ultrascale+ soc. Instead using MCDP6000 for RX and DP141 for TX, we use DP142 redriver for both the RX and TX ports on the board.


This is not supported. The Xilinx DP1.4 RX solution is VESA Displayport Compliant using a the Megachip MCDP6000 retimer. And this is the only configuration which is tested/verified

Please try with the supported solution first. If this is failing then we will be able to comment and help you.

But if you want to try with other equipment, then you need to do your own characterization and changes to the drivers/design. And no support from Xilinx is provided in this case


Florent
Product Application Engineer - Xilinx Technical Support EMEA
**~ Don't forget to reply, give kudos, and accept as solution.~**
Moderator
Moderator
316 Views
Registered: ‎10-04-2017

Hi 904860365@qq.com,

I want to follow up and clarify Florent's response. 
Florent is correct that the Xilinx solution is only tested/verified with the MCDP6000 and Xilinx does not support other solutions.
Because of this, if you find an issue with a supported platform we are able to escalate on our side. However, we will not be able to escalate any issue tested on your platform as the assumption is that the issue is due to the unsupported use-case.

 

That being said, please continue to use the forums as we can provide general debug guidance and the community may be able to help you debug issues that are outside of Xilinx support. 

-Sam

 

Don't forget to reply, kudo, and accept as solution.

Xilinx Video Design Hub
292 Views
Registered: ‎03-14-2019
Thanks a lot. It is the EDID problem, my two boards' DP ports successfully connected when I change the EDID of the RX one. Before that I simply assumed the pattern generator in TX can find the compliant video format since it worked fine with several EDIDs in a few testing monitors. And I used DP142 for both RX and TX, after I tuned the gain of DP142, there was no lane error any more.