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2U3
Explorer
Explorer
351 Views
Registered: ‎05-25-2020

Does AXI VDMA IP allow jitter in clock and data?

Hello,

I would like to store data from MIPI CSI-2 IP to DDR via AXI VDMA IP.

But clock and data of the MIPI data have jitter, as shown in a figure attached.

Periods between "Top of a Line" and "last" are all the same.
Periods between "last" and "Top of a Line" vary.
There is no clock during the periods between "last" and "Top of a Line."
Clock and data are perfectly synchronized.
A duty factor of the clock is around 25%.

Thank you.

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note_axi_dma_2.gif
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6 Replies
watari
Teacher
Teacher
297 Views
Registered: ‎06-16-2013

Hi @2U3 

 

Are you using non continuous clock mode in MIPI ?

If yes, would you change this mode to continuous clock mode ?

 

Best regards,

2U3
Explorer
Explorer
254 Views
Registered: ‎05-25-2020

Thank you for your advice, But I have not found a parameter for selecting the clock mode yet. And also, I do not understand what the clock mode is. If one select "continuous clock mode" in MIPI CSI-2 Receiver Subsystem IP, does the IP generate continuous clock?

 

Thank you.

 

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watari
Teacher
Teacher
227 Views
Registered: ‎06-16-2013

Hi @2U3 

 

Would you make sure whether your source device has this mode or not ?

 

Best regards,

karnanl
Xilinx Employee
Xilinx Employee
191 Views
Registered: ‎03-30-2016

Hello @2U3 

Just adding my comments ....

>I would like to store data from MIPI CSI-2 IP to DDR via AXI VDMA IP.
>But clock and data of the MIPI data have jitter, as shown in a figure attached.

If your MIPI source outputs clock with jitter, Xilinx MIPI CSI-2 RX will generate parallel clock (rxbyteclkhs) with jitter.

>Periods between "Top of a Line" and "last" are all the same.
>Periods between "last" and "Top of a Line" vary.
>There is no clock during the periods between "last" and "Top of a Line."
>Clock and data are perfectly synchronized.

Noted.


>A duty factor of the clock is around 25%.

Why duty factor of MIPI clock is around 25% ? This will violate MIPI D-PHY specification.

In MIPI D-PHY spec we have Data/Clock Timing spec as mentioned below.
It is difficult to follow spec requirement with clock duty factor around 25%.
DPHY_rx_setup_hold.png

>But I have not found a parameter for selecting the clock mode yet. And also, I do not understand what the clock mode is.

MIPI CSI-2 spec supports
    1. Continuous clock mode (mandatory mode)
   2. Non-continuous clock mode (optional mode)

So, every MIPI TX should be able to support continuous clock mode.

>If one select "continuous clock mode" in MIPI CSI-2 Receiver Subsystem IP, does the IP generate continuous clock?

Yes.


Thank you.
Leo


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2U3
Explorer
Explorer
141 Views
Registered: ‎05-25-2020

I made another new clock of 50% duty, and also generate a data from original data, which is synchronized to the new clock.

Then, VDMA seems to accept the new clock and data, and I will perform further check.

Thank you.

karnanl
Xilinx Employee
Xilinx Employee
53 Views
Registered: ‎03-30-2016

Hello @2U3 

I believe your issue is solved after using a new input clock with 50% duty ?!
If this is the case would you able to close this thread ?

Kind regards
Leo


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