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Way
Adventurer
Adventurer
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Registered: ‎10-19-2020

Enquiry on DP1.4 RX subsystem example design on AXI IIC controller

Hi,

I am looking at the example design DP1.4 RX Subsystem provided. I notice that the design contains two AXI IIC controller. One AXI IIC controller is added by selecting include IIC in DP Subsystem where another AXI IIC controller is added out of the DP RX subsystem. According to the user guide, the AXI IIC controller is used to control the MCDP6000 Retimer. However, I wonder why there are two AXI IIC controllers? Why two AXI IIC controllers are needed?

Attached snapshot shows the AXI IIC controller in both Top level block diagram design and DPRX subsystem.

TopLevel_Blockdiagram.PNG
DPRX_Subsystem.PNG
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florentw
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Registered: ‎11-09-2015

Hi @Way 

One IIC is used to control the retimer, the other is used to do the AUX-to-IIC features (used control to the EDID IP for example).

In the example design, the EDID is internal but it could also be an internal component.


Florent
Product Application Engineer - Xilinx Technical Support EMEA
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Way
Adventurer
Adventurer
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Registered: ‎10-19-2020

Hi @florentw ,

Thanks for your reply.

May I know if the IIC used to do the AUX-to-IIC features you mentioned is referring to EDID_IIC port that is already come with DisplayPort IP? Please correct me if I am wrong because I thought the EDID_IIC is the one convert AUX to IIC?

If we look at the DP1.4 RX example design, there are three IIC interfaces where EDID_IIC is embedded in DP Core, IIC is included in DP RX subsystem and another IIC is included in top level block diagram.

The top level block diagram contains one IIC called AXI_IIC_0. And, in the DisplayPort RX subsystem, there is another IIC called IIC included by selecting include IIC option in DisplayPort RX Subsystem parameter. These two IICs are connected to a i2c mux.

Looking at the software example provided, it seems like the AXI_IIC_0 on top level block diagram is used to send IIC data to configure VFMC IO Expander 1, LMK03318, IDT8T49N241 whereas the IIC in DisplayPort RX subsystem is used to control the retimer. However, I am wondering why can't just use one IIC controller instead? Please correct me if my understanding on the usage of each IIC is not correct.

Thank you in advance

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florentw
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Registered: ‎11-09-2015

HI @Way 

Yes sorry I missed one AXI IIC controller. Yes you are right the other is to control the clock.

I think you might need 2 different AXI IIC controller because you need to drive 2 different AXI interfaces.

You might be able to do with one AXI IIC with additional logic but I do not see anything wrong with having 2


Florent
Product Application Engineer - Xilinx Technical Support EMEA
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Way
Adventurer
Adventurer
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Registered: ‎10-19-2020

Hi @florentw 

Thanks for the clarification.

I just wondering all the IIC slave is located at the FMC modules. Why we need drive 2 different AXI interfaces?

Actually, I am kind of confuse on how these two AXI controller works together especially when both of these controllers are going through the I2C mux. Looking at the I2C Mux, it somehow using utility vector logic to arbitrate the signals from these two AXI controllers. As shown in the snapshot below,  the output enable signal for scl_t and sda_t from both IIC is ANDed while output signal scl_o and sda_o from both IIC is ORed.

In term of the hardware connection, I couldn't understand how the signal is being arbitrated between these two IIC. For example, if one IIC is active while the other is idle, this mean that the output enable signal (scl_t or sda_t) of one IIC is stay low while the other active IIC might be high and low. However, the scl_t or sda_t is ANDed which mean the output will still be zero. Wonder if you can help to elaborate on how this I2C mux working?

I2C_Mux.PNG
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florentw
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Registered: ‎11-09-2015

HI @Way 

There are 2 different one because one is part of the DP RX SS. It is expected while using the driver.

This is just designed like that as I guess the developers thought it would be easier for users (if you do not have a programmable clock you just have to remove one AXI IIC).

I am not expert in IIC but I assume the difference is the difference between the signals. One is the output enable and might be active low


Florent
Product Application Engineer - Xilinx Technical Support EMEA
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Way
Adventurer
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Registered: ‎10-19-2020

Hi @florentw ,

Thank you. Understand that the purpose is easier for users by implementing two AXI IIC.

However, I still couldn't get it on how the I2C mux is formed based on the AND gate and OR gate. I can reuse the I2C mux but I would like to understand the logic behind the I2C mux on how the i2c mux perform multiplexing onto the two different AXI IIC IP's signals.

 

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florentw
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Registered: ‎11-09-2015

HI @Way 

IOBUF.JPG

 

On the IBUFDS,  a logic-High on the T pin disables the output buffer. So you need to have the input IOBUF_IO_T to be low if you want to output data.

So it needs to be low if either i2c_a_scl_t or i2c_b_scl_t is low. This is why you have a logical AND.

Then the OR is for the data.


Florent
Product Application Engineer - Xilinx Technical Support EMEA
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