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Way
Participant
Participant
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Registered: ‎10-19-2020

Enquiry on MIPI CSI2 RX subsystem D-PHY Register Interface option

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Hi,

I am a little bit confuse on when should we enable the D-PHY register interface option in MIPI_CSI2 RX Subsystem. Looking at the example design provided from Xilinx ZCU102, this D-PHY register interface option is not enabled.

I look for some information in the forum and I just manage to found information like if we want to configure the IDELAY_TAP_VALUE dynamically (https://forums.xilinx.com/t5/Video-and-Audio/Errors-in-mipi-csi-2-rx/td-p/1147806), we would need to enable the D-PHY register interface option in MIPI_CSI2 RX Subsystem.

However, how about other DPHY register such as control register, INIT register and etc?  Can we access these register if D-PHY register interface option is not enable? When I am looking at the software application, the software application still able to read/write the DPHY register but I do not see this D-PHY register interface option is enabled in hardware design. Hence, I would like to ask when should we enable the D-PHY register interface option?

Below image is the D-PHY register option mentioned above.

 

dphy_reg_interface_option.PNG
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karnanl
Xilinx Employee
Xilinx Employee
84 Views
Registered: ‎03-30-2016

Hello @Way 

>I look for some information in the forum and I just manage to found information like if we want to configure the IDELAY_TAP_VALUE dynamically (https://forums.xilinx.com/t5/Video-and-Audio/Errors-in-mipi-csi-2-rx/td-p/1147806), we would need to enable the D-PHY register interface option in MIPI_CSI2 RX Subsystem.

Yes, your understanding above is correct.
# BTW, IDELAY_TAP_VALUE is a parameter for 7-series IP.
   Are you using UltraScale+ or 7-series device ?

>However, how about other DPHY register such as control register, INIT register and etc? Can we access these register if D-PHY register interface option is not enable?

You need to enable " D-PHY register interface" option, to access those registers.
# I believe, in MIPI CSI-2 RX Example Design for ZCU102, MIPI D-PHY RX's register is not accessed.

Kind regards.
Leo

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karnanl
Xilinx Employee
Xilinx Employee
85 Views
Registered: ‎03-30-2016

Hello @Way 

>I look for some information in the forum and I just manage to found information like if we want to configure the IDELAY_TAP_VALUE dynamically (https://forums.xilinx.com/t5/Video-and-Audio/Errors-in-mipi-csi-2-rx/td-p/1147806), we would need to enable the D-PHY register interface option in MIPI_CSI2 RX Subsystem.

Yes, your understanding above is correct.
# BTW, IDELAY_TAP_VALUE is a parameter for 7-series IP.
   Are you using UltraScale+ or 7-series device ?

>However, how about other DPHY register such as control register, INIT register and etc? Can we access these register if D-PHY register interface option is not enable?

You need to enable " D-PHY register interface" option, to access those registers.
# I believe, in MIPI CSI-2 RX Example Design for ZCU102, MIPI D-PHY RX's register is not accessed.

Kind regards.
Leo

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Way
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Participant
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Registered: ‎10-19-2020

Hi @karnanl 

Thanks for the information. I am using 7 series device.

After went through the software application for MIPI CSI-2 RX Example Design for ZCU102, it seems like this example did not access the Dphy register. It was my mistake when I first looking at the example.

Also, I am having some issue on read/write the MIPI DPHY register and I posted another questions(https://forums.xilinx.com/t5/Video-and-Audio/Issue-with-read-and-write-the-MIPI-DPHY-register/td-p/1210590). Wonder if do you have any suggestion regarding the issue mentioned in that question?