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Explorer
Explorer
1,329 Views
Registered: ‎05-04-2014

HDMI RX/TX cpll bonded mode

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Hi

We have customized board and device is Kintex 7 FBG676 -2. For passing HDMI repeater CTS, we must set Rx and Tx  to CPLL bonded mode. If tmds clock is over 80 MHz, the test pass. However, tmds clock is under 80 MHz, Tx doesn't work.

We find a note as below highlighted in yellow

 

Video_Phy.PNG

Is there any method to solve this problem?

 

Thanks,

Sitting

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Explorer
Explorer
1,185 Views
Registered: ‎05-04-2014

Hi ,

I  implemented a method to pass the HDMI CTS. 

I changed the PLL layout to Rx-cpll/Tx-qpll when HDMI Rx detect tmds clock is under 80 MHz, and if tmds clock is over 80 MHz, I changed the PLL layout to Rx/Tx cpll bonded mode.

 

 

Thanks

Sitting

 

 

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Moderator
Moderator
1,280 Views
Registered: ‎10-04-2017

Hi @sitting,

 

This is a known limitation of bonded mode.

The TX side is clocked using oversampling of the TMDS clock, while the RX side uses the NI-DRU. If the user sends the NI-DRU clock to the TX there will be an issue. 

Is the QPLL available in your design and is the resolution that you are targeting supported by the QPLL?

See table 3-10 in PG230. 

 

If so, you can automatically switch either your TX or RX from the CPLL -> CPLL to QPLL->CPLL or CPLL->QPLL mode for all resolutions that require the DRU clock.

 

Regards,

Sam

 

 

 

Don't forget to reply, kudo, and accept as solution.

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Explorer
Explorer
1,270 Views
Registered: ‎05-04-2014

@samk,

QPLL of GTX is not available in HDMI CTS. One of HDMI CTS item would check lowest and highest frame rate on every resolution. For example, 1920*1080 @60 Hz(TMDS clock is 148.5 MHz),  the lowest frame rate is 59.64 Hz(TMDS clock is 147.609 MHz), the highest frame rate is 60.3 Hz(TMDS clock is 149.2425 MHz). For 147.609 MHz, QPLL doesn't support it.

 

One of HDMI CTS item specification are as below:Image.pngImage1.png

We are still looking for other solutions to solve this problem.

 

Thanks

Sitting

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Xilinx Employee
Xilinx Employee
1,253 Views
Registered: ‎08-02-2007

Hi @sitting

Unfortunately this limitation has been explicitly documented in PG230, that's the way it works :

Capture.JPG

Moderator
Moderator
1,226 Views
Registered: ‎10-04-2017

Hi @sitting,

 

As Xud has mentioned this is a known Limitation.

With this in mind, my first thoughts are to either use 2 VPHYs and 2 banks to accomplish a CPLL-> CPLL solution or to use a newer part that does not have the frequency limitations

 

Don't forget to reply, kudo, and accept as solution.

Xilinx Video Design Hub
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Explorer
Explorer
1,186 Views
Registered: ‎05-04-2014

Hi ,

I  implemented a method to pass the HDMI CTS. 

I changed the PLL layout to Rx-cpll/Tx-qpll when HDMI Rx detect tmds clock is under 80 MHz, and if tmds clock is over 80 MHz, I changed the PLL layout to Rx/Tx cpll bonded mode.

 

 

Thanks

Sitting

 

 

View solution in original post