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Nireeksha
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Registered: ‎04-22-2020

HDMI and 10G deign

  • Can I build a design with combination of HDMI In and out and 10G in one?
  • Also combination of HDMI In and Out and SDI In and Out?
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xud
Xilinx Employee
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Registered: ‎08-02-2007

Nireeksha
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Thank you.

So my another doubt  is , whether HDMI and SDI combination is possible?

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xud
Xilinx Employee
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Registered: ‎08-02-2007

@Nireeksha 

It's possible as some users use FPGA to implement SDI and HDMI converter.

HDMI and SDI are transport standard. HDMI resolution and color information is defined in CEA-861 protocol, while SDI's resolution is defined in SMPTE standard.

Depending on your application, if you need to convert between two different protocols, then you need to investigate further on those standard, and implement necessary mapping between video stream and audio stream. If both SDI in/out are independent to HDMI in/out, it is a bit easier.

Nireeksha
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Thanks for the info!

In my design consisting of combination of HDMI and 10G , I'm getting an error while synthesis run.

Error : video frame buffer write module is not found.

Error : video processing system module is not found.

May I know what is the reason for this?

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xud
Xilinx Employee
Xilinx Employee
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Registered: ‎08-02-2007

@Nireeksha 

Can you try to use Linux machine? As framebuffer, TPG, VPSS requires path that is longer than the window's path restrictions, it may fail in synthesis.

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Nireeksha
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Ok !! 

Tried with Linux. In which it shows that video frame buffer has illegal characters.

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xud
Xilinx Employee
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Registered: ‎08-02-2007

@Nireeksha 

Can you provide bd tcl by using "write_bd_tcl test.tcl"? If it fails, please PM me with your email address, I will try to get your zipped project, and try to reproduce the issue at my end.

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Nireeksha
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Now while compiling there is an error appearing that video frame buffer write , video processing ips before we give synthesis run , we need to run command syth_ip or generate_target,t hen this appears in the log

given command 'ap_source' returned error code
    while executing
"source [lindex $::argv 1] "
    ("uplevel" body line 1)
    invoked from within
"uplevel \#0 { source [lindex $::argv 1] } "

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xud
Xilinx Employee
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Registered: ‎08-02-2007

@Nireeksha 

VPSS is based on HLS. Please have a look at forum post below :

https://forums.xilinx.com/t5/High-Level-Synthesis-HLS/Vivado-hls-co-simulation-fail/td-p/515665

It seems the issue is still to do with path. If you change path, open project on Linux machine, remove VPSS, and add a fresh one, does it help?

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Nireeksha
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I haven't opened the project in Linux. This issue is to be seen in windows itself where it was created initially.

Is this due to the hierarchy.since I have created hierarchy in the design under which I have added the hdmi IN blocks and another separate hierarchy for out

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xud
Xilinx Employee
Xilinx Employee
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Registered: ‎08-02-2007

@Nireeksha 

Yes, hierarchy is one factor, also it's due to the way how IP is named in the block design.

All the HLS based IPs (eg. VPSS, TPG. Video Multi-Scaler, frame Buffer) have this problem.

Please try to keep your window project path as short as possible, block design name as short as possible, IP name as short as possible, don't create subsystem in your block design, it may help.

We have documented this issue in https://www.xilinx.com/support/answers/71804.html

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Nireeksha
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Thank you.Finally the issue is solved.That was mainly due to hierarchy , it was taking long path.

Found a new error while implementation run

  • [Place 30-640] Place Check : This design requires more RAMB18 and RAMB36/FIFO cells than are available in the target device. This design requires 414 of such cell types but only 288 compatible sites are available in the target device. Please analyze your synthesis results and constraints to ensure the design is mapped to Xilinx primitives as expected. If so, please consider targeting a larger device.

This this a  limitation?

 

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xud
Xilinx Employee
Xilinx Employee
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Registered: ‎08-02-2007

@Nireeksha 

This error tells your design uses too many Block Rams. You can have a look at utilization report and see which IP uses block RAMs, probably you can use Ultra RAM, depending on your device type.

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Nireeksha
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So I have decided  to analyse the BRAM utilisation by each module so as to analyse the issue of RAMB shortage.

Can you please brief about how to analyse by knowing the BRAM utilisation of each module what is the root cause.

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Nireeksha
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Hello,

I need to know about how do can we make use of block generator ip so as to divide the memory utilisation between BRAM and URAM.

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xud
Xilinx Employee
Xilinx Employee
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Registered: ‎08-02-2007

@Nireeksha 

it's more related to Tool's issue, rather than IP issue. 

You can click report Utilization after open Synthesized design, then you should be able to figure out the BRAM ultilization.

report_utilization.JPG

 

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Nireeksha
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Registered: ‎04-22-2020

Thanks for the info. That helped a lot.I could solve the memory issue.

Currently I'm facing another issue in the HDMI+10 design,Error is as  follows:The design requires more GTE4_COMMO than available in the target device.The design requires 2 such type cell , but only one is available in the device.

May i know what's the reason behind this issue

 

 

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xud
Xilinx Employee
Xilinx Employee
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Registered: ‎08-02-2007

@Nireeksha 

Are you trying to share SDI with HDMI in the same quad? 

I think each quad can only have one GT common block. If you share SDI with HDMI in the same quad, it may cause the problem, as Video PHY contains Common block and UHD-SDI GT has common block, you need to remove one of them. 

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Nireeksha
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I have used 10G/25G ethernet subsystem.

Could be please attach few snapshots related to it.

 

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xud
Xilinx Employee
Xilinx Employee
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Registered: ‎08-02-2007

@Nireeksha 

10G/25G Ethernet Subsystem IP needs to use QPLL too. If you have questions related to this IP, please post a new thread to Ethernet board : https://forums.xilinx.com/t5/Ethernet/bd-p/CONN

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Nireeksha
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OK! Thanks

The address  of PL DDR4 in the design I assigned as 4_0000_0000 -> 4_3FFF_FFFF.But while testing only till 4_0000_0000 -> 4_0000_0007 can be read.Why so?

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xud
Xilinx Employee
Xilinx Employee
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Registered: ‎08-02-2007

@Nireeksha 

That is a Processor Design question and how they have there addressing done. That would require a post in the Processor Design forum.

samk
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Registered: ‎10-04-2017

Hi @Nireeksha,

 

As Xu mentioned the DDR question will be best on the https://forums.xilinx.com/t5/Memory-Interfaces-and-NoC/bd-p/MIG forum.

Is your original question answered? If so, can you please mark the post that answered your question as the solution?

 

For additional questions for Audio/Video, please create a new thread so that each question can be answered. If you have questions, please see the Community Forums Guidelines.

Thank you,

Sam

Don't forget to reply, kudo, and accept as solution.

Xilinx Video Design Hub
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Nireeksha
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Hello,

May I know when vivado 2020.1 release is expected.

 

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xud
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@Nireeksha 

It's planned to be released on the 3nd of June.

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Nireeksha
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Ok Thanks.

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Nireeksha
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Registered: ‎04-22-2020

Hello,

I have create HDMI IN and OUT combinational design. While implementation there is error coming up as 

" No clocks specified . please specify clocks using -clock, -fall_clock , rise_clock options [bd_8000_v_tc_0_clocks.xdc6].

As per my understanding I need to mention the differential clock in the XDC file as "create_clock -period 1.200 -name si5324_clk_p_in [get_ports si5324_clk_p_in] ".

But My doubt is how is the period need to be analysed.On what basis this has to be metioned.

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xud
Xilinx Employee
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Registered: ‎08-02-2007

@Nireeksha 

If original issue is resolved, can you mark accept solution to close this thread? 

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