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Contributor
Contributor
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Registered: ‎01-06-2016

Half Duplex HDMI

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I was just wondering if it's possible to use the same pins for both input and output HDMI in a half-duplex fashion?

This is for an Artix7 FPGA.

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Moderator
Moderator
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Registered: ‎11-09-2015

Hi @rtfinch  and @karnanl 

I think there are multiple confusions here.

The first one is on the HDMI solution you, @rtfinch, are tying to use. Xilinx HDMI IP solution, the HDMI 1.4/2.0 Subsystems solution is working on the Gigabit Transceivers (GT). This is what @karnanl  thinks you are using. However, you are probably only looking for a solution which can output 1080p thus through the serial IOs. Typically you might be using an IP from Digilent? Or something equivalent?
HDMI or DVI through the serial IO is something I have done through my article Video Series 23: Generate a video output on Pynq-Z2 HDMI out. I am right in my understanding.

Then the second confusion is that @karnanl thinks that you are talking about the same GT but with a different pin. I.e. each GT has a TX and an RX. So it is possible to use both TX and RX however this is not the same pin.

TMDS signals cannot be bidirectional as per UG471 p103 so I am not sure this is doable

 


Florent
Product Application Engineer - Xilinx Technical Support EMEA
**~ Don't forget to reply, give kudos, and accept as solution.~**

View solution in original post

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Xilinx Employee
Xilinx Employee
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Registered: ‎03-30-2016

Hello @rtfinch 

Yes it is possible, since GTP has 2 PLLs in one quad (PLL0 and PLL1).
Please see PG230 Chapter1. (Please ensure that your device is -2 or -3 speed-grade device.)

GTP_HDMI.png


See also chapter4 regarding implementation and supported video format (in Table 85)

GTP_HDMI_2.png
PG235/PG236 Chapter6 does describe a procedure to generate an Example Design for HDMI, but unfortunately Example Design for GTP is not available.


Regards
Leo

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Contributor
Contributor
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Registered: ‎01-06-2016

Okay, I coded a test, and there's an error message during implementation that the TMDS33 standard is only either input or output. I'm looking up other standards now.

The part is a -2 part. The signals aren't connected to the gigabit transceivers. 

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Xilinx Employee
Xilinx Employee
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Registered: ‎03-30-2016

Hello @rtfinch 

Did you try to generate any Example Design from PG235/PG236 ?

Please also the following post : https://forums.xilinx.com/t5/Serial-Transceivers/TMDS-signalling-on-ZCU104/m-p/1081193#M7154
You do not need to use TMDS_33 standard for HDMI clock pins. GTP input/output does not need IO standard definition too.
Please notice that you need to use level shifter/Retimer device in your system to use HDMI IP.


Regards
Leo

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Moderator
Moderator
254 Views
Registered: ‎11-09-2015

Hi @rtfinch  and @karnanl 

I think there are multiple confusions here.

The first one is on the HDMI solution you, @rtfinch, are tying to use. Xilinx HDMI IP solution, the HDMI 1.4/2.0 Subsystems solution is working on the Gigabit Transceivers (GT). This is what @karnanl  thinks you are using. However, you are probably only looking for a solution which can output 1080p thus through the serial IOs. Typically you might be using an IP from Digilent? Or something equivalent?
HDMI or DVI through the serial IO is something I have done through my article Video Series 23: Generate a video output on Pynq-Z2 HDMI out. I am right in my understanding.

Then the second confusion is that @karnanl thinks that you are talking about the same GT but with a different pin. I.e. each GT has a TX and an RX. So it is possible to use both TX and RX however this is not the same pin.

TMDS signals cannot be bidirectional as per UG471 p103 so I am not sure this is doable

 


Florent
Product Application Engineer - Xilinx Technical Support EMEA
**~ Don't forget to reply, give kudos, and accept as solution.~**

View solution in original post

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Contributor
Contributor
219 Views
Registered: ‎01-06-2016

Thanks, Yes I was looking for lower speed I/O. I was referring to a slightly modified HDMI IP core from Digilent (the core works). I separated the inputs and outputs to separate pins now.