How to interface MIPI CSI-2 IP with external deserializer

[bojankoce]

Hello guys,

We intend to use Xilinx MIPI IP cores (only receiver subsystem) implemented in Zynq Ultrascale+ MPSoC in order to accept video data from GMSL or FPD Link III deserializers with MIPI CSI-2 output. 

I know that Ultrascale+ architectures have enhanced MIPI D-PHY support capabilities i.e. IBUFDS_DPHY input buffers that will allow us to directly connect MIPI CSI-2 data lanes from serializer to FPGA HP I/O bank. There will be no need for any external resistor since we can internally include 100Ohms resistor as an option. Correct?

What about the MIPI CSI-2 clock signals? What kind of I/O standard should we use for the MIPI CSI-2 clock lane?

What data rate per lane can we have with such enhanced MIPI D-PHY capabilities in Ultrascale+ families? Can we have 1.5Gbps per lane?

Thanks in advance for your time and effort.

Sincerely,

Bojan.

[florentw · Accepted solution]

Hi @bojankoce,

There will be no need for any external resistor since we can internally include 100Ohms resistor as an option. Correct?

> Yes this is correct

What about the MIPI CSI-2 clock signals? What kind of I/O standard should we use for the MIPI CSI-2 clock lane?

> For ZU+, the xdc constraint are automatically generated by the core and you can do the IO planning in the IP configuration GUI.

Edit: All the MIPI pins (clock + data) need to use the D_PHY IO standard on US+

What data rate per lane can we have with such enhanced MIPI D-PHY capabilities in Ultrascale+ families? Can we have 1.5Gbps per lane?

> Yes as per pg232:

Kind Regards,

Florent