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wbyjerry
Adventurer
Adventurer
578 Views
Registered: ‎07-29-2013

How to simulate Video Processing Subsystem inside my design?

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I want to use Video Processing Subsystem IP in my design.

But there is no way to cofigure the register by myself as the PG231 noted.

Note: Control of the video processing pipe is only supported through the Video Processing Subsystem driver. The register map is provided for debug purposes only. 

I only want to scale video up by Video Processing Subsystem IP.

I already have written the verilog testbench but don't know how to configure the register to let the ip run in my simulation environment. 

https://forums.xilinx.com/t5/Video/Register-space-of-Video-Processing-Subsystem-make-me-confused/m-p/1040167#M28753

Is there any easy way to configure the register and stream in video to verify this IP without the actual board?

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florentw
Moderator
Moderator
521 Views
Registered: ‎11-09-2015

Hi @wbyjerry 

Kindly note that simulation is not supported for the Video Processing Subsystem.

With that said, I see 2 way you could have it working:

  • Check in HW for the AXI4-Lite transactions which are executed and replicate the same with an AXI VIP. But it might be tricky to make it to work
  • Generate the design + application for a microblaze. Then with the elf file, you should be able to run the simulation for the microblaze. However, this is not something that I have done so I am not exactly sure about the exact steps.

My recommendation is to do your testings diretly in HW. It is much easier.

Regards


Florent
Product Application Engineer - Xilinx Technical Support EMEA
**~ Don't forget to reply, give kudos, and accept as solution.~**

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florentw
Moderator
Moderator
522 Views
Registered: ‎11-09-2015

Hi @wbyjerry 

Kindly note that simulation is not supported for the Video Processing Subsystem.

With that said, I see 2 way you could have it working:

  • Check in HW for the AXI4-Lite transactions which are executed and replicate the same with an AXI VIP. But it might be tricky to make it to work
  • Generate the design + application for a microblaze. Then with the elf file, you should be able to run the simulation for the microblaze. However, this is not something that I have done so I am not exactly sure about the exact steps.

My recommendation is to do your testings diretly in HW. It is much easier.

Regards


Florent
Product Application Engineer - Xilinx Technical Support EMEA
**~ Don't forget to reply, give kudos, and accept as solution.~**

View solution in original post

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wbyjerry
Adventurer
Adventurer
513 Views
Registered: ‎07-29-2013

 

Thanks for your reply. @florentw 

I still have one question. I could read the driver in the example roughly. But some function I don't need that. Like log function.

I don't know how to migrate the driver from example to my special design without V_TPG and V_TC. And I want call the drivers easyly.

Is there anyplace to explain how to use the drivers of VPSS more deeply than Appx.c in PG231 .

 

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florentw
Moderator
Moderator
504 Views
Registered: ‎11-09-2015
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