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Contributor
Contributor
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Registered: ‎01-27-2019

How to write vivado sdk to implement hdmi frequency doubling?

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I need to receive a 30Hz video stream from HDMI in and export it as 60Hz through HDMI out.

I would like to use double buffer so that

cycle    from  hdmi in                                                          to  hdmi out

1            write to  buffer 1 (top half of frame 1)           read from buffer  2(whole frame 1)

2            write to buffer 1 (bottom half of frame1 )    read from buffer 2(whole frame 1 again )

3            write to  buffer 2 (top half of frame 2)             read from  buffer1(whole frame 2)

4           write to buffer 2 (bottom half of frame 2)    read from buffer 1(whole frame 2 again)

I don't know how to implement above in  Vivado SDK.  Please advise.

Also, is there any examples?

.....

 

 

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Moderator
Moderator
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Registered: ‎11-09-2015

Hi @dr.elichan 

It will not work with only 2 buffers. You need to use at least 3 buffers so you have one buffer to switch from/to.

If you work with only 2 buffers: when the write of a frame is over on buffer 1, it will not be able to switch to buffer 2 because the read is happening. Same for the read.


Florent
Product Application Engineer - Xilinx Technical Support EMEA
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Contributor
Contributor
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Registered: ‎01-27-2019

@watari,

Thank you for giving me the VDMA references. I enjoy reading them.

I can barely achieve the frequency doubling by using only one buffer. But  I want to use double buffers(say buffer1, buffer2) so that read and write will never interfere with each other.
To do so, I need to read each buffer with one repeat so that

write   buffer2-------------->buffer1------------->buffer2---------------->buffer1

read    buffer2->buffer2->buffer1->buffer1->buffer2->buffer2->buffer1->buffer1

Is there any simple way to implement it?

 

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Contributor
Contributor
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Registered: ‎01-27-2019

write buffer1-------------->buffer2------------->buffer1---------------->buffer2

read buffer2->buffer2->buffer1->buffer1->buffer2->buffer2->buffer1->buffer1
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Teacher
Teacher
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Registered: ‎06-16-2013

Hi @dr.elichan 

 

Would you try gen-lock function on VDMA ?

Refer the following URL, if you want to know details about gen-lock.

 

https://www.xilinx.com/support/documentation/ip_documentation/axi_vdma/v6_2/pg020_axi_vdma.pdf#page=39

 

Best regards,

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Moderator
Moderator
147 Views
Registered: ‎11-09-2015

Hi @dr.elichan 

@watari is right. If you select the correct genlock configuration for the AXI VDMA then the read interface can simply repeat the last frame so you can double the frame rate. The following topic might give you some information:

https://forums.xilinx.com/t5/Video-and-Audio/FPS-converter/m-p/1006283/highlight/true#M26947

However, one thing you need to be aware is that using this method you might not have good visual result (because you are only repeating frames). And you might want to consider building a motion compensation block. There was a discussion about this:
https://forums.xilinx.com/t5/Video-and-Audio/video-frame-rate-conversion-motion-compensation-e-t-c/td-p/1116786

Regards

 


Florent
Product Application Engineer - Xilinx Technical Support EMEA
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Contributor
Contributor
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Registered: ‎01-27-2019

Thank you to @florentw and @watari . I now understand that genlock is the most promising approach. However, I still have some difficulties to understand exactly what genlock mechanism is doing.

Assuming a double buffer situation with (buffer1 and buffer2)  and with genlock enabled 

will vdma keep repeatingly reading buffer2 if buffer1 is still being written?

 

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Moderator
Moderator
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Registered: ‎11-09-2015

Hi @dr.elichan 

It will not work with only 2 buffers. You need to use at least 3 buffers so you have one buffer to switch from/to.

If you work with only 2 buffers: when the write of a frame is over on buffer 1, it will not be able to switch to buffer 2 because the read is happening. Same for the read.


Florent
Product Application Engineer - Xilinx Technical Support EMEA
**~ Don't forget to reply, give kudos, and accept as solution.~**

View solution in original post

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Contributor
Contributor
97 Views
Registered: ‎01-27-2019

s2mm (dynamic genlock master) ----> mm2s(dynamic genlock slave)

Assuming that it is in a triple buffer mode, is it correct to assume that

1) s2mm write will jump to write the next buffer if  the ad-hoc buffer is currently read by mm2s

2) mm2s read will jump to reading the next buffer if the ad-hoc  buffer  is currently written by s2mm.

3) irrespective of whatever writing speed or reading speed, mm2s  will be guaranteed to be able to read some data successfully from one of the three buffers. (irrespective of how choppy the video output will be)

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Moderator
Moderator
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Registered: ‎11-09-2015

HI @dr.elichan 

Yes this is correct


Florent
Product Application Engineer - Xilinx Technical Support EMEA
**~ Don't forget to reply, give kudos, and accept as solution.~**
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