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gmoore
Contributor
Contributor
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Registered: ‎08-29-2016

Implementation Issue with MIPI Rx Dphy on Ultrascale+

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Hi,

 

My design makes use of the MIPI dphy IP. I am using a 2-lane MIPI design, generated with 'shared logic in core', generated out of context per ip. 

 

I am getting an error at the implementation step - below is an example of the error, and the full implementation log is attached. 

ERROR: [DRC BSCK-6] BITSLICE_CONTROL_RIU_CLK_ACTIVE: BITSLICE_CONTROL mipi_dphy_rx_2l_inst/inst/mipi_dphy_rx_2l_rx_support_i/slave_rx.mipi_dphy_rx_2l_rx_hssio_i/inst/top_inst/bs_ctrl_top_inst/BITSLICE_CTRL[4].bs_ctrl_inst RIU_CLK pin requires a clock signal to function. It cannot be tied-off or unconnected.

 

I used the instantiation template auto-generated by the IP generator to instantiate the module, and all signals are connected. Could you provide guidance as to how to solve this error ? 

 

regards

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samk
Moderator
Moderator
1,248 Views
Registered: ‎10-04-2017

Hi @gmoore,

 

Here are some general steps for debugging a disconnected pin error.

 

1. Open up the Synthesized design schematic and verify that the pin is connected. This may mean tracing the logic back through the design to the top level interface.

 

2. If the pin is not connected, was it connected initially or was the logic synthesized out?

 

3. Check the source code or block design make sure it is connected and then check the Synthesis log to see if the connection was removed or trimmed.

 

4. In the synthesized design if the pin was connected, is it connected to the source that you believe it is? In this case a clock signal?

 

 

Regards,
Sam

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samk
Moderator
Moderator
1,249 Views
Registered: ‎10-04-2017

Hi @gmoore,

 

Here are some general steps for debugging a disconnected pin error.

 

1. Open up the Synthesized design schematic and verify that the pin is connected. This may mean tracing the logic back through the design to the top level interface.

 

2. If the pin is not connected, was it connected initially or was the logic synthesized out?

 

3. Check the source code or block design make sure it is connected and then check the Synthesis log to see if the connection was removed or trimmed.

 

4. In the synthesized design if the pin was connected, is it connected to the source that you believe it is? In this case a clock signal?

 

 

Regards,
Sam

Don't forget to reply, kudo, and accept as solution.

Xilinx Video Design Hub

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mik3l3_hdl
Participant
Participant
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Registered: ‎08-15-2019

Hello,

 

i got the same type of error and the following is the message i got:

[DRC BSCK-6] BITSLICE_CONTROL_RIU_CLK_ACTIVE: BITSLICE_CONTROL dacInterface/dataClockOut/inst/top_inst/bs_ctrl_top_inst/BITSLICE_CTRL[7].bs_ctrl_inst RIU_CLK pin requires a clock signal to function. It cannot be tied-off or unconnected.

I followed your general step and the RIU_CLK pin is connected to a clock signal, specifically to the output of the clock generator. (??)

What i could do to fix this?


Thanks

Regards

 

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florentw
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Registered: ‎11-09-2015

HI @mik3l3_hdl 

Our Community Help has a tip that might help you : Tip: If the message is older than 6-12 months, please post a new message rather than adding to the existing thread. Your inquiry will have a better chance of being picked up by an expert if it is a new topic.

https://forums.xilinx.com/t5/help/faqpage/faq-category-id/posting#posting

I would suggest you create a new topic on the appropriate board


Florent
Product Application Engineer - Xilinx Technical Support EMEA
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