Implementation error on the AXI Stream to Video Out

[tsjorgensen]

I get the following error message during the implementation phase of my small video design.

[Opt 31-67] Problem: A LUT4 cell in the design is missing a connection on input pin I3, which is used by the LUT equation. This pin has either been left unconnected in the design or the connection was removed due to the trimming of unused logic. The LUT cell name is: pl_inst/gen_video.vid_stream_out_inst/inst/SYNC_INST/FSM_sequential_state[3]_i_2.

None of the pins to or from the core seems to be unconnected, even vid_field_id I've connected to a read register even though I don't use it.

It is not a blocked design, cores are instantiated in VHDL:

    gen_video : if true generate
    signal aresetn                      : std_logic;
    signal vid_tdata                    : std_logic_vector(23 downto 0);
    signal vid_tvalid                   : std_logic;
    signal vid_tready                   : std_logic;
    signal vid_tuser                    : std_logic;
    signal vid_tlast                    : std_logic;
    signal vid_tkeep                    : std_logic_vector(2 downto 0);
    signal vid_tstrb                    : std_logic_vector(2 downto 0);
    signal vid_tid                      : std_logic;
    signal vid_tdest                    : std_logic;
    signal vid_data                     : std_logic_vector(23 downto 0);
    signal vtg_vsync                    : std_logic;
    signal vtg_hsync                    : std_logic;
    signal vtg_vblank                   : std_logic;
    signal vtg_hblank                   : std_logic;
    signal vtg_active_video             : std_logic;
    signal vtg_field_id                 : std_logic;
    signal vtg_ce                       : std_logic;
        
    begin
    
        aresetn     <= not areset;
    
        vid_stream_out_inst : v_axi4s_vid_out_comp
        port map (
            aclk                    => aclk,
            aclken                  => '1',
            aresetn                 => aresetn,
            s_axis_video_tdata      => vid_tdata,
            s_axis_video_tvalid     => vid_tvalid,
            s_axis_video_tready     => vid_tready,
            s_axis_video_tuser      => vid_tuser,
            s_axis_video_tlast      => vid_tlast,
            fid                     => '0',
            vid_io_out_ce           => '1',
            vid_io_out_clk          => vid_clk,
            vid_io_out_reset        => areset,
            vid_active_video        => vid_active_video_o,
            vid_vsync               => vid_vsync_o,
            vid_hsync               => vid_hsync_o,
            vid_vblank              => vid_vblank_o,
            vid_hblank              => vid_hblank_o,
            vid_field_id            => vid_field_id,
            vid_data                => vid_data_o,
            vtg_vsync               => vtg_vsync,
            vtg_hsync               => vtg_hsync,
            vtg_vblank              => vtg_vblank,
            vtg_hblank              => vtg_hblank,
            vtg_active_video        => vtg_active_video,
            vtg_field_id            => vtg_field_id,
            vtg_ce                  => vtg_ce,
            locked                  => vid_locked,
            overflow                => vid_overflow,
            underflow               => vid_underflow,
            fifo_read_level         => vid_fifo_read_level,
            status                  => vid_status
        );

        v_tc_comp_inst : v_tc_comp
        port map (
            clk                     => vid_clk,
            clken                   => '1',
            s_axi_aclk              => aclk,
            s_axi_aclken            => '1',
            gen_clken               => vtg_ce,
            hsync_out               => vtg_hsync,
            hblank_out              => vtg_hblank,
            vsync_out               => vtg_vsync,
            vblank_out              => vtg_vblank,
            active_video_out        => vtg_active_video,
            resetn                  => aresetn,
            s_axi_aresetn           => aresetn,
            s_axi_awaddr            => m_axilite_m2s_busarray(11).awaddr(8 downto 0),
            s_axi_awvalid           => m_axilite_m2s_busarray(11).awvalid,
            s_axi_awready           => m_axilite_s2m_busarray(11).awready,
            s_axi_wdata             => m_axilite_m2s_busarray(11).wdata,
            s_axi_wstrb             => m_axilite_m2s_busarray(11).wstrb,
            s_axi_wvalid            => m_axilite_m2s_busarray(11).wvalid,
            s_axi_wready            => m_axilite_s2m_busarray(11).wready,
            s_axi_bresp             => m_axilite_s2m_busarray(11).bresp,
            s_axi_bvalid            => m_axilite_s2m_busarray(11).bvalid,
            s_axi_bready            => m_axilite_m2s_busarray(11).bready,
            s_axi_araddr            => m_axilite_m2s_busarray(11).araddr(8 downto 0),
            s_axi_arvalid           => m_axilite_m2s_busarray(11).arvalid,
            s_axi_arready           => m_axilite_s2m_busarray(11).arready,
            s_axi_rdata             => m_axilite_s2m_busarray(11).rdata,
            s_axi_rresp             => m_axilite_s2m_busarray(11).rresp,
            s_axi_rvalid            => m_axilite_s2m_busarray(11).rvalid,
            s_axi_rready            => m_axilite_m2s_busarray(11).rready,
            irq                     => cpu_irq(14),
            fsync_in                => '0',
            fsync_out               => open
        );
        
        v_tpg_comp_inst : v_tpg_comp
        port map (
            s_axi_ctrl_awaddr       => m_axilite_m2s_busarray(12).awaddr(7 downto 0),
            s_axi_ctrl_awvalid      => m_axilite_m2s_busarray(12).awvalid,
            s_axi_ctrl_awready      => m_axilite_s2m_busarray(12).awready,
            s_axi_ctrl_wdata        => m_axilite_m2s_busarray(12).wdata,
            s_axi_ctrl_wstrb        => m_axilite_m2s_busarray(12).wstrb,
            s_axi_ctrl_wvalid       => m_axilite_m2s_busarray(12).wvalid,
            s_axi_ctrl_wready       => m_axilite_s2m_busarray(12).wready,
            s_axi_ctrl_bresp        => m_axilite_s2m_busarray(12).bresp,
            s_axi_ctrl_bvalid       => m_axilite_s2m_busarray(12).bvalid,
            s_axi_ctrl_bready       => m_axilite_m2s_busarray(12).bready,
            s_axi_ctrl_araddr       => m_axilite_m2s_busarray(12).araddr(7 downto 0),
            s_axi_ctrl_arvalid      => m_axilite_m2s_busarray(12).arvalid,
            s_axi_ctrl_arready      => m_axilite_s2m_busarray(12).arready,
            s_axi_ctrl_rdata        => m_axilite_s2m_busarray(12).rdata,
            s_axi_ctrl_rresp        => m_axilite_s2m_busarray(12).rresp,
            s_axi_ctrl_rvalid       => m_axilite_s2m_busarray(12).rvalid,
            s_axi_ctrl_rready       => m_axilite_m2s_busarray(12).rready,
            ap_clk                  => aclk,
            ap_rst_n                => '1',
            fid                     => open,
            fid_in                  => (others => '0'),
            interrupt               => cpu_irq(15),
            m_axis_video_tvalid     => vid_tvalid,
            m_axis_video_tready     => vid_tready,
            m_axis_video_tdata      => vid_tdata,
            m_axis_video_tkeep      => vid_tkeep,
            m_axis_video_tstrb      => vid_tstrb,
            m_axis_video_tuser(0)   => vid_tuser,
            m_axis_video_tlast(0)   => vid_tlast,
            m_axis_video_tid(0)     => vid_tid,
            m_axis_video_tdest(0)   => vid_tdest
        );
        
    end generate;

File is set to VHDL2008. Simulation seems to work.

Can anyone spot the problem?

Thank you in advance.

[xilinxacct]

@tsjorgensen 

Do any of these solutions provide any insight?

https://forums.xilinx.com/t5/AXI-Infrastructure/Opt-31-67/m-p/890594#M1679
https://forums.xilinx.com/t5/Implementation/Opt-31-67-with-custom-IP-with-AXI-Stream-bus/m-p/935922#M23597
https://forums.xilinx.com/t5/Implementation/Opt-31-67-Problem-A-LUT2-cell-in-the-design-is-missing-a/m-p/914500#M23002
https://forums.xilinx.com/t5/Implementation/Opt-31-67-Problem-A-LUT3-cell-in-the-design-is-missing-a/m-p/858002#M20833
https://forums.xilinx.com/t5/Implementation/Opt-31-67/m-p/890211#M22471
https://forums.xilinx.com/t5/Implementation/OPT-31-67-How-to-get-removed-logic-report-when-opt-design-fails/m-p/692275#M15131
https://forums.xilinx.com/t5/Implementation/opt-31-67-error-when-using-ip-AXI-Stream-FIFO-as-receive-only/m-p/714004#M15867
https://forums.xilinx.com/t5/Implementation/Opt-31-67-Problem-what-does-this-mean/m-p/642989#M13075
https://forums.xilinx.com/t5/PCI-Express/Opt-31-67-Problem-A-LUT2-cell-in-the-design/m-p/849918#M10616

Hope that helps

If so, please mark as solution accepted. Kudos also welcomed. :-)

[tsjorgensen · Accepted solution]

Seems that if I connect the vtg_field_id to a read-register it can run implementation. I don't know why this is, as far as I know I don't need the vtg_field_id if I don't use interlacing.

Anyway it seems my problem has gone. Thank you @xilinxacct for the links.