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Contributor
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Registered: ‎08-28-2019

Issue with a Test pattern Generator Designed in HLS

Hello,

I used the video series(14,15) to write a test pattern generator in HLS (generate a Red Frame).

When I connect to the module to the AXI stream to video out IP , VTC and VGA, The required frame is displayed. But, when I first write to the DRAM throuh VDMA and read , before connecting to the IPs mentioned above, no data is displayed. So, I did some digging and realized VDMA is (s2mm interface) produced a VDMAIntr error. But I have done all the necessary configurations for hsize,vsize and stride. The IP does not have the axi lite interface, just  the ap_start which is connected to the a constant '1'. 

Is there anything I am doing wrong?

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Registered: ‎11-09-2015

Hi @baring42read 

When debbugging the AXI VDMA, make sure you are reading twice the status register to make sure the issue is consistent as per what I mention in the following article https://forums.xilinx.com/t5/Design-and-Debug-Techniques-Blog/Video-Series-25-Debugging-issues-on-the-AXI-VDMA-IP/ba-p/941372

Are you sure the debug module is correctly counting the number of pixels per line? Could it be that in your TPG, the height and width are inverted (you are generating 600*800 instead of 800*600)?


Florent
Product Application Engineer - Xilinx Technical Support EMEA
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Registered: ‎08-28-2019

Hello @florentw 

 

When debbugging the AXI VDMA, make sure you are reading twice the status register to make sure the issue is consistent 

I have actually cross checked the debugging and there is no VDMA Internal Error. However, there is still no data being written to the DRAM. This is because, Tready is still constantly LOW.  Going through the PG020  document, I realized there is something on page  79 about Tready being low when alignment constraints are not met. However, Alignment Transfer is enabled so this can possibly not be the error.

Are you sure the debug module is correctly counting the number of pixels per line? Could it be that in your TPG, the height and width are inverted (you are generating 600*800 instead of 800*600)?

Yes I am sure because I was able to Display the data through the VGA port without VDMA in the Design. That is, TPG to  Axi Stream to Video and to VGA.

I don't know exactly what could be the problem

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Registered: ‎11-09-2015

Hi @baring42read 

Make sure the S2MM is still running by reading reg 0x30

There is also the following condition on the VDMA (as per pg020):

S2MM channel does not transfer any data on the memory side and after a few stream transactions s_axis_s2mm_tready goes Low.
Answer: Ensure that s_axis_s2mm_tkeep is tied to 1 when the Streaming Master IP does not support it

Also, you might want to check the interface to the memory. Maybe if tready is low there, then tready might be low on the AXI4S


Florent
Product Application Engineer - Xilinx Technical Support EMEA
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Registered: ‎08-28-2019

Hello @florentw 

1. The streaming IP (TPG) has Tkeep  and the bit size is equal to that on the s2mm Interface.

2. The 0x30  address was configured  

Xil_Out32(XPAR_AXIVDMA_0_BASEADDR + 0x30, 0x8B)
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Registered: ‎11-09-2015

Hi @baring42read 

If the halted bit is asserted at some point, the run/stop bit of the reg 0x30 might be deasserted so please check the value of reg 0x30, do not only rely on what you have configured


Florent
Product Application Engineer - Xilinx Technical Support EMEA
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Registered: ‎08-28-2019

Hello @florentw  I have checked the 0x30h register and it 's as expected: And the halted bit is never asserted.

I am beginning to wonder if it caused by the fact that the ap_start is constantly connected to a constant '1'.

 

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Registered: ‎11-09-2015

Hi @baring42read 

Do you have tvalid high? If that is the case, then the TPG is producing data so I do not think this is an issue with ap_start.

Unless the IP is not generating new SOF (tuser = 1) or EOL (tlast = 1)?


Florent
Product Application Engineer - Xilinx Technical Support EMEA
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Registered: ‎08-28-2019

Hello @florentw 

Tvalid is '1' but the Tuser and Tlast are never asserted . Also I tried a few scenarios

1. Connecting custom  IP to axis stream to video out and VGA: This works as expected and the frame is displayed.

2. Connecting  custom IP to RGB2YCbCR IP, axis stream to video out and VGA: The locked signal is never asserted and the 3th bit  of the status signal is asserted. According to the document, this means VTG EOL (End Of Line) Leading. This means that the EOL signal (hsync) from the Video Timing Generator happens before the EOL signal from the AXI4-Stream (tlast). In other words, the horizontal size configured in the VTG is smaller than the horizontal size coming on the AXI4-Interface.

The sync of the signals is lost as more signals are connected to the pipeline, after the custom IP.

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Registered: ‎11-09-2015

Hi @baring42read 

Can you configure the TPG on a small side, ex 640*480. Try to capture the tlast and tuser and make sure you have enough data.

Or you can try to cross-check to TPG output with the debug module from AR#59790.

My suspicion is that there is a tlast missing. Probably the last one of the frame. Maybe try to capture multiple tuser with an ILA


Florent
Product Application Engineer - Xilinx Technical Support EMEA
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Registered: ‎11-09-2015

Hi @baring42read 

Do you have any update on this? Were you able to make any progress?


Florent
Product Application Engineer - Xilinx Technical Support EMEA
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Registered: ‎08-28-2019

Hello @florentw  I have not made any changes. will get back to you when I do.

Thank you

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I think the problem is, the data is being sent continuously. After Tlast, the TPG has to wait for a few clocks before sending data again. This  kind of mimics the behavior of the  TPG in the IP catalog

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Registered: ‎11-09-2015

Hi @baring42read 

Did you make it work by waiting few cycles after tlast. I would not expect this has an impact


Florent
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Yes, I waited for about 5 iterations after Tlast before generating tye pixels of the next line and it worked