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Voyager
Voyager
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Registered: ‎07-06-2016

LVDS camera interface deserialization question

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Hello,

I need to interface a camera sensor LVDS data stream with a ZYNQ device, the signal/data format is:

- 1 Differential clock.

- 1 differential data line. The data format is a 12 bit  packet per clock in SDR mode.

What I have to do/use in Vivado to get and deserialize those 12bits in parallel?

I had a look to this application but only talks abut 1:7 deserialization... does it mean that is not possible for greater data packages? 

Thanks.

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Mentor
Mentor
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Registered: ‎06-16-2013

Re: LVDS camera interface deserialization question

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Hi @joseer

 

Is this signal edge aligned signal ?

If yes, how about this way ?

 

1. Generate clock (x12) and do phase shift (1.666[ns]) by PLL

40ns / 12 = 3.333[ns]

2. Latch signal by generated clock.

3. Convert signal from serial data to parallel via shift register

4. Remap paralleled signal or separate paralleled signal to what you get.

 

Best regards,

 

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Teacher
Teacher
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Registered: ‎07-09-2009

Re: LVDS camera interface deserialization question

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What experiance do you have ? What tools are you used to using ?
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Scholar
Scholar
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Registered: ‎06-10-2008

Re: LVDS camera interface deserialization question

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The mentioned application note also states:

Each I/O logic tile in the 7 series FPGAs contains an 8-bit ISERDES and an 8-bit OSERDES. The ISERDES and OSERDES from two adjacent blocks (master and slave) can be cascaded to give a 10-bit or 14-bit block. This gives the possibility of ISERDES input ratios from 1:2 to 1:8 inclusive, 1:10 and 1:14 for single data rate (SDR) operation, and 1:2, 1:4, 1:6, 1:8, 1:10 and 1:14 for double data rate (DDR) operation. The OSERDES has output ratios from 2:1 to 8:1 inclusive, 10:1 and 14:1 for SDR operation, 2:1, 4:1, 6:1, 8:1, 10:1 and 14:1 for DDR I/O clocks.


So it looks like it supports a lot more, but 1:12 was too difficult.

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Teacher
Teacher
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Registered: ‎07-09-2009

Re: LVDS camera interface deserialization question

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I think the App was originally using code for camera link, which is 7:1
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Voyager
Voyager
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Registered: ‎07-06-2016

Re: LVDS camera interface deserialization question

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Thanks for the replies,

I did work in projects using Vivado tools (design,IP integrator for custom HDL IPs, HLS..etc) with different image sensors for different applications but always in parallel.

Now, I need to interface a sensor with a LVDS 12 bits output differential data lane and differential clock.

Is there any workaround to solve this? 

 

 

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Mentor
Mentor
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Registered: ‎06-16-2013

Re: LVDS camera interface deserialization question

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Hi @joseer

 

In my experience, camera sensor has th following interfaces.

 

1. Camera link

2. MIPI CSI

3. Parallel

4. Other specific interface

 

A)

According this thread, 1 and 3 are already mentioned by some people.

 

Would you refer following url, if you want 1's suggestion.

https://www.xilinx.com/support/documentation/application_notes/xapp585-lvds-source-synch-serdes-clock-multiplication.pdf

 

B)

BTW, as you mentioned before, if your camera sensor doesn't have any control signals, would you refer tthe following url ?

 

https://www.xilinx.com/support/documentation/application_notes/xapp524-serial-lvds-adc-interface.pdf

 

If you explain more detail about your sensor's interface, I reply it.

 

I guess your sensor's interface  is A) or MIPI CSI.

If it is MIPI CSI, you can use Xilinx's MIPI CSI Rx IP.

 

But I can not decide it. Because of it is not enough information.

So, would you explain more detail ?

 

Best regards,

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Visitor
Visitor
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Registered: ‎07-17-2017

Re: LVDS camera interface deserialization question

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What we have done in the past is run the SERDES as 6 bit words.  Then every other cycle take the two 6 bits words to make a 12 bit word. 

Also, with serial channels, you also need to implement a word alignment/framing synchronization, where a known and unambiguous pattern is transmitted, and the framing is stepped bit by bit, till the pattern matches.  Typically the image sensors either send such a pattern out in idle, or can be configured to send them.  I believe the series 7 does support bitslip to adjust the bit framing., but you may also need to step the 6 bit words.

 

 

 

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Voyager
Voyager
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Registered: ‎07-06-2016

Re: LVDS camera interface deserialization question

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Thanks for the replies.

@watari

Yes, it would be easier if I had one of those standard interfaces (Camera link, MIPI...) you pointed, but unfortunately it's more a specific/custom one. First of all the LVDS mode used is the Case 1 described here, "The data stream is a multiple of the rate of the incoming clock, and the clock signal is used as a framing signal for the received data"

The camera format is 12 bit packet (one each rising edge clock), where:

Bit[0] -->  Start bit '1'

Bit[1 -8] --> pixel data[0-7]

Bit[9] -->    Line Valid    

Bit[10] -->    Frame Valid    

Bit[11] -->    Stop bit '0' 

I had a look already to the documents you pointed, but I couldn't see how to use SERDES to read 12bits with this LVDS case....

@@highfreq

yes, Selecting SERDES 6 bit (I'm using selectI/O wizard in Vivado) it will generate a clock 6 times the input clock and theoretically only it will be read the 6 even bits.

Would it be possible to use une selectI/O to read the 6 even bits and other to read the odd ones? but I guess a delay has to be implemented for the second one, not sure how can be done to align properly both groups of 6.

 

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Mentor
Mentor
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Registered: ‎06-16-2013

Re: LVDS camera interface deserialization question

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Hi @joseer

 

Could you show us your target frequency ?

 

I guess you use PLL as phase shift (1/12) and two 6bit serdes.

 

Best regards,

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Voyager
Voyager
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Registered: ‎07-06-2016

Re: LVDS camera interface deserialization question

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Hi @watari,

 

The target frequency is the pixel clock 25MHz. I'm using two 6 bit SERDES but I'm not sure how to align the data to have even and odd bits at same time....

 

Thanks.

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Mentor
Mentor
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Registered: ‎06-16-2013

Re: LVDS camera interface deserialization question

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Hi @joseer

 

Is this signal edge aligned signal ?

If yes, how about this way ?

 

1. Generate clock (x12) and do phase shift (1.666[ns]) by PLL

40ns / 12 = 3.333[ns]

2. Latch signal by generated clock.

3. Convert signal from serial data to parallel via shift register

4. Remap paralleled signal or separate paralleled signal to what you get.

 

Best regards,

 

View solution in original post

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Voyager
Voyager
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Registered: ‎07-06-2016

Re: LVDS camera interface deserialization question

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Hi @watari,

 

Yes, the data is aligned to the clock rising edge.

What you are suggesting is basically get 'manually' the 12 bits package instead using SERDES,  get the input pixel clock and generate a x12 clock with PLL and use it to deserialize the12 bit package. So how could I get in Vivado a only signal from differential lines, i.e the clock from clk_P and clk_N and Data_line form data_P data_N? or should I use only the positive line?

Thanks.

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Mentor
Mentor
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Registered: ‎06-16-2013

Re: LVDS camera interface deserialization question

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Hi @joseer

 

You can use IBUFDS to receive differential signal.

Also I suggest using internal termination for signal integrity.

 

Best regards 

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Voyager
Voyager
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Registered: ‎07-06-2016

Re: LVDS camera interface deserialization question

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Hi @watari,

 

I'll try what you suggested and see how it goes. Unfortunately I can't use internal termination as the bank is powered at 3.3V so I have to find the way to attach an external one... 

Thanks.

Best regards.

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Visitor
Visitor
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Registered: ‎07-17-2017

Re: LVDS camera interface deserialization question

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@joseer wrote:

Thanks for the replies.

 

yes, Selecting SERDES 6 bit (I'm using selectI/O wizard in Vivado) it will generate a clock 6 times the input clock and theoretically only it will be read the 6 even bits.

Would it be possible to use une selectI/O to read the 6 even bits and other to read the odd ones? but I guess a delay has to be implemented for the second one, not sure how can be done to align properly both groups of 6.


logic [5:0] first_half, second_half;
logic phase, valid_phase, data_valid
logic [11:0] full_word;

assign full_word = {first_half, second_half};  //MSB or LSB first?
assign data_valid = phase == valid_phase;
always_ff @(posedge clk) begin
  phase <= ~phase
  first_half <= SERDES_OUTPUT;
  second_half <= first_half;
end


I'm not sure what you mean by 6 even bits.  The serdes will be reading 6 consecutive bits each cycle, a first_half and second_half, as you can see in the code above.

You just need to align the 6 bits, via bitslip.  Both phases will have the same alignment.  You also need to determine which is the valid phase.  You have a total of 12 phases to step through. 

With a 25MHz pixel rate, you would be running at a 50Mhz clock, which isn't pushing things.  Two cycles per pixel gives flexibility in handling data stream.

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