09-23-2020 09:36 AM
Hi,
I am using MIPI CSI-2 RX Subsystem IP v4.1 in my design and IMX586 camera sensor.
In the IP GUI we are configuring the line rate as 2400Mbps.
I just wanted to know ,
1) if we configure the sensor for line rates lesser than 2400Mbps whether the IP is able to take care of this?
2)Whether the line rate configuration in sensor and the IP should be same?
Looking for the response.
With regards,
Thejashree
09-23-2020 11:54 PM
You might want to search for answers before asking your questions. With the rights keywords you might find the solution. It might save you some time not to have to ask.
For example in your question, I just try to google with the following keywords:
MIPI dynamic lane rate xilinx forums
This is the search results I am getting.
The first 2 results have the answer:
https://forums.xilinx.com/t5/Video-and-Audio/MIPI-D-PHY-CSI-2-receiver-change-line-rate/td-p/822351
https://forums.xilinx.com/t5/Video-and-Audio/CSI-2-RX-dynamic-linerate/td-p/1089293
Regards,
09-23-2020 11:54 PM
You might want to search for answers before asking your questions. With the rights keywords you might find the solution. It might save you some time not to have to ask.
For example in your question, I just try to google with the following keywords:
MIPI dynamic lane rate xilinx forums
This is the search results I am getting.
The first 2 results have the answer:
https://forums.xilinx.com/t5/Video-and-Audio/MIPI-D-PHY-CSI-2-receiver-change-line-rate/td-p/822351
https://forums.xilinx.com/t5/Video-and-Audio/CSI-2-RX-dynamic-linerate/td-p/1089293
Regards,
09-25-2020 03:39 AM
Hi @florentw ,
Thank you for the information provided.
We were aware of the thing that IP does not support dynamic line rate change. Our concern was , if IP receives lower line rate than the configured in GUI from sensor, whether it is able to receive the data and work properly.
Anyways , now we are clear that this is just a trail and error method and its safe if we maintain different bit files for the different line rates.
With regards,
Thejashree
09-25-2020 03:42 AM
Yes this is what is explained in the topic I mentioned.
This might work if the lane rates are not too far but this is not tested supported by Xilinx
09-25-2020 03:55 AM