MIPI CSI-2 Rx Subsystem (4.1) CRC output on TUSER not working?

[malstew]

We are trying to use the CRC bits output on TUSER[95:80] for checking data integrity downstream from the MIPI CSI-2 RX IP but when we look at the CRC output, bits 95/94 don't toggle -- I would expect it to randomly toggle. 

According to documentation CRC might not be accurate in the following cases:  "In error scenarios like abrupt termination due to soft reset, disabling the core while packet transfer in progress, line buffer in full condition, word count of received packet is greater than the actual payload".  I don't see these conditions on the device -- although I am not sure where to check for "word count of received packet> actual payload"  

Here is the Register status: 

0x0000: 0x00000001
0x0004: 0x0000001B
0x0008: 0x00000000
0x000C: 0x00000000
0x0010: 0xDF9E0000
0x0014: 0x00000000
0x0018: 0x00000000
0x001C: 0x00000000
0x0020: 0x00000000
0x0024: 0x80020000
0x0028: 0x00000000
0x002C: 0x00000000
0x0030: 0x00000000

Device Config:

Any suggestions would be appreciated. 

Thanks,
Malcolm

[karnanl · Accepted solution]

Hello @malstew 

Unfortunately this is a known issue for MIPI CSI-2 RX Subsystem.
Please see also : https://www.xilinx.com/support/answers/75325.html

This issue is fix in IP generated by Vivado 2020.2.
If you are using Vivado 2020.1 , you can use patch from AR#75325 to fix this issue.
If you are using an older Vivado version, please migrate to Vivado 2020.2 ( or Vivado 2020.1).

Kind regards
Leo