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markramona
Explorer
Explorer
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Registered: ‎12-12-2018

MIPI CSI RX Subsystem Synchronous clock for AXI and Video

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We are building a system with the MIPI CSI RX subsystem that utilizes the same clock for the AXI and the Video output.

 

However, during compilation, we keep getting warnings

WARNING: [XPM_CDC_SINGLE: TCL-1000] The source and destination clocks are the same.
Instance: design_1/mipi_inst/inst/rx/inst/AXI_LITE.reg_inf/xpm_single_05
This will add unnecessary latency to the design. Please check the design for the following:
1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules.
2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
[/opt/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl:5]

 

While these warnings seem safe to ignore, it would be nice to reduce usage count where we don't need them..

 

There doesn't seem to be an obvious configuration parameter that sets the clocks synchronous in the internal XPM macros.

 

What is the recommended solution for this?

 

Could we get a hotfix release that allows us to set the relation between the clocks:

 

  1. Same
  2. Synchronous and ratio
  3. Asynch and CDC stages.
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karnanl
Xilinx Employee
Xilinx Employee
359 Views
Registered: ‎03-30-2016

Hello @markramona 

I have been discussed your request with internal teams again,
They agree to add this "Synchronous AXI-lite and Video Stream" option for future IP improvement.

But unfortunately, we don't have notifications for internal ticket system that can be share with Forum user.
So please refer to MIPI CSI-2 RX IP "changelog" or PG232 to know when this feature is implemented.

Something like this :

Kind regards
Leo


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markramona
Explorer
Explorer
602 Views
Registered: ‎12-12-2018

To be clear, these are the listed available parameters from the MIPI module in 2020.2

 

ALLOWED_SIM_MODELS
ALLOWED_SIM_TYPES
BASE_BOARD_PART
BOARD
BOARD_CONNECTIONS
CAN_IP_GENERATE
CLASS
COMBINED_SIM_MODEL
CONFIG.AXIS_TDATA_WIDTH
CONFIG.AXIS_TDEST_WIDTH
CONFIG.AXIS_TUSER_WIDTH
CONFIG.CLK.CLKOUTPHY_IN.INSERT_VIP
CONFIG.CLK.DPHY_CLK_200M.INSERT_VIP
CONFIG.CLK.LITE_ACLK.INSERT_VIP
CONFIG.CLK.RXBYTECLKHS.INSERT_VIP
CONFIG.CLK.VIDEO_ACLK.INSERT_VIP
CONFIG.CLK_LANE_IO_LOC
CONFIG.CLK_LANE_IO_LOC_NAME
CONFIG.CMN_FIFO_RD_EN_CNTRL
CONFIG.CMN_INC_IIC
CONFIG.CMN_INC_VFB
CONFIG.CMN_NUM_LANES
CONFIG.CMN_NUM_PIXELS
CONFIG.CMN_PROJ_FAMILY
CONFIG.CMN_PXL_FORMAT
CONFIG.CMN_VC
CONFIG.CSIRXSS_S_AXI.INSERT_VIP
CONFIG.CSI_BUF_DEPTH
CONFIG.CSI_CONTROLLER_REG_IF
CONFIG.CSI_EMB_NON_IMG
CONFIG.C_CAL_MODE
CONFIG.C_CLK_IO_SWAP
CONFIG.C_CLK_LANE_IO_POSITION
CONFIG.C_CLK_LP_IO_SWAP
CONFIG.C_CSI2RX_DBG
CONFIG.C_CSI_EN_ACTIVELANES
CONFIG.C_CSI_EN_CRC
CONFIG.C_CSI_FILTER_USERDATATYPE
CONFIG.C_CSI_OPT1_REGS
CONFIG.C_DATA_LANE0_IO_POSITION
CONFIG.C_DATA_LANE1_IO_POSITION
CONFIG.C_DATA_LANE2_IO_POSITION
CONFIG.C_DATA_LANE3_IO_POSITION
CONFIG.C_DL0_IO_SWAP
CONFIG.C_DL0_LP_IO_SWAP
CONFIG.C_DL1_IO_SWAP
CONFIG.C_DL1_LP_IO_SWAP
CONFIG.C_DL2_IO_SWAP
CONFIG.C_DL2_LP_IO_SWAP
CONFIG.C_DL3_IO_SWAP
CONFIG.C_DL3_LP_IO_SWAP
CONFIG.C_DPHY_LANES
CONFIG.C_DPHY_MODE
CONFIG.C_EN_BG0_PIN0
CONFIG.C_EN_BG0_PIN6
CONFIG.C_EN_BG1_PIN0
CONFIG.C_EN_BG1_PIN6
CONFIG.C_EN_BG2_PIN0
CONFIG.C_EN_BG2_PIN6
CONFIG.C_EN_BG3_PIN0
CONFIG.C_EN_BG3_PIN6
CONFIG.C_EN_CLK300M
CONFIG.C_EN_CNTS_BYTE_CLK
CONFIG.C_EN_CSI_V2_0
CONFIG.C_EN_EXDESIGNS
CONFIG.C_EN_TIMEOUT_REGS
CONFIG.C_EN_VCX
CONFIG.C_ESC_TIMEOUT
CONFIG.C_EXDES_BOARD
CONFIG.C_EXDES_CONFIG
CONFIG.C_EXDES_FMC
CONFIG.C_FIFO_RD_EN_CONTROL
CONFIG.C_HS_LINE_RATE
CONFIG.C_HS_SETTLE_NS
CONFIG.C_HS_TIMEOUT
CONFIG.C_IDLY_GROUP_NAME
CONFIG.C_IDLY_TAP
CONFIG.C_INIT
CONFIG.C_IS_7SERIES
CONFIG.C_IS_VERSAL
CONFIG.C_LPRX_DISABLE_EXTPORT
CONFIG.C_MIPI_SLV_INT
CONFIG.C_OOC_VID_CLK
CONFIG.C_RCVE_ALT_DESKEW_SEQ
CONFIG.C_RCVE_DESKEW_SEQ
CONFIG.C_SHARE_IDLYCTRL
CONFIG.C_STRETCH_LINE_RATE
CONFIG.Component_Name
CONFIG.DATA_LANE0_BYTE
CONFIG.DATA_LANE0_IO_LOC
CONFIG.DATA_LANE0_IO_LOC_NAME
CONFIG.DATA_LANE1_BYTE
CONFIG.DATA_LANE1_IO_LOC
CONFIG.DATA_LANE1_IO_LOC_NAME
CONFIG.DATA_LANE2_BYTE
CONFIG.DATA_LANE2_IO_LOC
CONFIG.DATA_LANE2_IO_LOC_NAME
CONFIG.DATA_LANE3_BYTE
CONFIG.DATA_LANE3_IO_LOC
CONFIG.DATA_LANE3_IO_LOC_NAME
CONFIG.DPHYRX_BOARD_INTERFACE
CONFIG.DPHY_PRESET
CONFIG.DPY_EN_REG_IF
CONFIG.DPY_LINE_RATE
CONFIG.HP_IO_BANK_SELECTION
CONFIG.RST.LITE_ARESETN.INSERT_VIP
CONFIG.RST.VIDEO_ARESETN.INSERT_VIP
CONFIG.SupportLevel
CONFIG.USE_BOARD_FLOW
CONFIG.VFB_TU_WIDTH
CONFIG.VIDEO_OUT.INSERT_VIP
CORE_REVISION
DCP_RESOURCE_DATA
DEFINITION_SOURCE
DELIVERED_TARGETS
DESIGN_TOOL_CONTEXTS
FAMILY
INTERNAL_MEMORY_ADDRESS
IPDEF
IP_CORE_CONTAINER
IP_DIR
IP_FILE
IP_OUTPUT_DIR
IP_SHARED_DIR
IS_BD_CONTEXT
IS_LOCKED
IS_NATIVE
KNOWN_TARGETS
LOCK_DETAILS
NAME
PART
REQUIRES_VIP
SCOPE
SELECTED_SIM_MODEL
STALE_TARGETS
SUPPORTED_TARGETS
SUPPORTS_MODREF
SW_VERSION
SYSTEMC_LIBRARIES
UNSUPPORTED_SIMULATORS
UPGRADE_RESULT
UPGRADE_VERSIONS
USED_LICENSE_KEYS
USER_LOCKED
USE_IP_SHARED_DIR
XPM_LIBRARIES

 

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karnanl
Xilinx Employee
Xilinx Employee
548 Views
Registered: ‎03-30-2016

Hello @markramona 

This is not a bug. So, your understanding is correct this warning message can be ignored.
These CDC FFs are necessary since most users may use MIPI CSI-2 RX with asynchronous clock for AXI-lite and Video Stream.

For your use-case (user with synchronous clock), please ignore this message. It will not causing any harm to your design.

Kind regards,
Leo


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markramona
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Registered: ‎12-12-2018

Thanks @karnanl 

I understand that "ignoring" warnings seems like an acceptable solution, but it is not an ideal solution long term.

Hunting down warnings is an effective way of tightening up designs, and ensuring that systems are reproducible beyond isolated builds.

I really would like to request an update that would allow us to specify, at configuration time the correct configuration that would avoid the CDCs.

CDCs add delays, resource utilization, and the warnings become noise in our build logs.

The MIPI CSI Subsystem seem like an actively developed IP at Xilinx (major updates in the last few versions of Vivado). Therefore, it seems like it would be a useful configuration to add to your support matrix.

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karnanl
Xilinx Employee
Xilinx Employee
444 Views
Registered: ‎03-30-2016

Hello @markramona 

Let me discuss this with internal teams and give you feedback on this.
Please wait.

Kind regards,
Leo


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karnanl
Xilinx Employee
Xilinx Employee
416 Views
Registered: ‎03-30-2016

Hello @markramona 

I've discussed this internal teams.
Pardon me but since this is not a show-stopper issue and MIPI CSI-2 RX is created for system with asynchronous clock for AXI-lite and Video Stream,
We don't have any plan to add this feature for now.

>CDCs add delays, resource utilization, and the warnings become noise in our build logs.

Yes this CDC FFs will use up some resources, but this is necessary for the IP to support a wide range of AXI-lite/Video clock frequency use cases.

BTW, if you have concern on warning messages, would you able to suppress Vivado message using the following command ?
       set_msg_config -suppress -id {[XPM_CDC_SINGLE: TCL-1000]}
or perhaps converting the message into INFO
       set_msg_config -id {[XPM_CDC_SINGLE: TCL-1000]} -new_severity INFO

Thanks & regards
Leo


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markramona
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Registered: ‎12-12-2018

Ok, Understood that it isn't in the current roadmap.

 

It would be super useful. Look at the netlist, there seems to be a chain of 7 FF that do the CDC crossing. Not very ideal when the IP is replicated a few times.

 

Are we able to subscribe to any notifications to your ticketing systems to get updates if/when this is implemented.

 

Best,

 

Mark

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karnanl
Xilinx Employee
Xilinx Employee
360 Views
Registered: ‎03-30-2016

Hello @markramona 

I have been discussed your request with internal teams again,
They agree to add this "Synchronous AXI-lite and Video Stream" option for future IP improvement.

But unfortunately, we don't have notifications for internal ticket system that can be share with Forum user.
So please refer to MIPI CSI-2 RX IP "changelog" or PG232 to know when this feature is implemented.

Something like this :

Kind regards
Leo


------------------------------------------------------------------------------------------------
Don’t forget to reply, kudo, and accept as solution.
If starting with Versal take a look at our Versal Design Process Hub and our Versal Blogs
Versal Example Designs : LINK
>>------------------------------------------------------------------------------------------------

View solution in original post

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markramona
Explorer
Explorer
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Registered: ‎12-12-2018

Thanks Leo! Understood, we will keep an eye out for the update.

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