MIPI CSI2 D-PHY to FPGA Zynq

[maggilgi]

Dear Xilinx,

I have a problem with setup of MIPI CSI 2 communication. The D-PHY I want to use is the minimum PHY configuration consists of a clock and one data signals.

The DPHY uses two wires per data lane and two wires for the clock lane in unidirectional transmission

The lane operate in a high-speed (HS) signaling mode for fast-data traffic and low-power (LP)

signaling mode.

I want to implement the passive resistor network to create the compatible D-PHY with FPGA ZYNQ 7030 where I’ve instantiated MIPI CSI-2 Receiver Subsystem v3.0 ip core.

As the first matter I want to verified if the physical connections is right or not.

The MIPI D-PHY TX Device is an AWR1243 and I listed below the output signals and the CSI-2 DPHY Electrical Specification:

DP[0]

DN[0]

Differential data Out – Lane 0

DP[1]

DN[1]

Differential data Out – Lane 1

DP[2]

DN[2]

Differential data Out – Lane 2

DP[3]

DN[3]

Differential data Out – Lane 3

CLKP

CLKN

Differential clock Out

HSPTX

VOD (HS transmit differential voltage): 200mV

VCM (HS transmit static common-mode voltage): 200mV

VOHHS (HS output high voltage): 360mV (max)

LPTX

VOL: 50mV

VOH: 1.2V

Frequency bus of 75 MHz.

I’ve notice that the interface of master doesn’t have i2C connection as shown in your XAPP894 document:

It can be a problem?

 I’ve implemented the same resistor network for each data and clock lines as depicted in the following figure

The port used in the Zynq7030 are in Bank 35 (HP bank port)

 I’ve direct connected all HS and LP signals to Mipi D-PHY ip core (MIPI CSI-2 Receiver Subsystem v3.0)

The following figures shows the DP[0] –yellow DPN[0] –green signals and CLKP –yellow CLKN –green signals at the output port of Master device with the resistor network shown before.

 

Please could you confirm to me that the connections are ok?

Best regards,

[karnanl]

Dear @maggilgi

As shown below, your signal electrical level should be okay.

HSTX

VOD (HS transmit differential voltage): 200mV

VCM (HS transmit static common-mode voltage): 200mV

VOHHS (HS output high voltage): 360mV (max)

LPTX

VOL: 50mV

VOH: 1.2V

Could you please explain your screen-capture ?? ( What is A, B,and C ? I believe D is the HS period from your sensor)

-Is B a short-packet ?

-If A and C are LP-period, I cannot see any LP-11, LP-10, LP-00 transition between LP-->HS period.

 I am expecting LP-11, LP-10, LP-00 transition between LP-->HS period. Could you please check this transition on your HW ?

If you already implemented MIPi CSI-2 RX on your FPGA, could you please share your MIPI CSI-2 RX & MIPI D-PHY register dump ? Please share your XCI file too.

Thanks & regards

Leo

[florentw]

HI @maggilgi,

Do you have any updates on this? Was @karnanl's answer enough for you?

If your question is answered or your issue is solved, please mark the response which helped as solution (click on the button "Accept as solution" below the reply)

If this is not solved/answered, please reply in the topic giving more information on your current status.

Best Regards,

[maggilgi]

Dear Leo,

It seems that there are problems at MIPI CSI-2 TX.

I tried to measure the voltage in the following case:

1) Keeping the CSI-2 signal floating

2) With 100 ohm termination between P-N signal of data and clock as shown the below figure ( I've renamed DP-DN signal CSI2_TXP[0] and CSI2_TXM[0]):

In both measures the maximum voltage is 0.8V while in the second case the LP10 state disappears one.

I've measured the signals in J1.56 and J1.58 points with an oscilloscope.

The first figure below shows the voltage level without any termination (all signal are floating) while in the second one I've placed 100 ohm termination between CSI2_TXP[0] and CSI2_TXM[0] and connect them to FPGA.

As highlighted in the second figure the LP signals integrity are compromised and the status LP10 is disappeared.

Could you tell me what am i doing wrong? How can I convert the CSI-2 singals to HS and LP signal without destroy LP10 state?

I also tried to disconnect the TX from Receiver (FPGA) and place the 100ohm resistor between P-N signals without any ither connections. I've got the same results and measurements to the P and N signals.

Than you for your time. 

Best regards

[karnanl · Accepted solution]

Hello @maggilgi

1. Your implementation seems to be very different compared to the XAPP894 guideline
Please notice that XAPP894 is using different I/O standard (HSUL12 for LP pins & LVDS_25 for HS pins)

2. Just some suggestions .
- Could you use UltraScale+ devices to receive MIPI CSI-2 signals ?
  Xilinx UltraScale+ devices support MIPI D-PHY signal natively.
  Please contact your local distributor if you are looking for an US+ evaluation board.
- If you prefer to use 7-series devices, could you please try to use external MIPI PHY devices ?
  (For example Meticom devices http://www.meticom.com/page2/page17/MC20901.html )

Thanks & regards
Leo

[maggilgi]

Dear Leo,

I work only with Zynq 7015.

what I want to highlighted with the previous reply is that the voltage measurement doesn't depend on the standard port on LP signal.

I've measured the signals on P and N pins of R9 with the oscilloscope without any other connections.

If I disconnect the MIPI receiver (all signals MIPI TX bus are floating) and i connect only R9 termination with 150 ohm (with 100 ohms the same results) the LP10 signal disappears (as showhn in the previous figures). I've measured the voltage between R9 resistor with oscilloscope.

It seems the problem is not the connections between the TX and RX but only in the TX because the signal integrity worse if i connect only R9 differential termination.

How is it possible?

I'll try to implement the network with HSUL standard as you suggested but for me it will be strange if it should work by connecting LP singal to FPGA while keeping it floating  not.

Thanks and best regards

Luigi

[karnanl]

Hello Luigi
Thank you for sharing the result.

1. Pardon me but I do not have experience using resistor-network solution as mentioned in XAPP894.
I cannot give you a good advice on it.
2. We do see some customers with 7-series shipped their product. (all of them is using external D-PHY devices)
I always suggest customer with 7-series device to use PHY componenct provided by Meticom. (or even using US+ devices with native D-PHY support)
3. PG232 appendix A mentioned that all 7-series interop-test was tested using Meticom device.
XAPP894 is release in 2014 even before Xilinx release its MIPI D-PHY IP. (at Vivado 2015.1)

Let me ask around if someone from developer team has tested using resistor network, BTW, what kind of sensor are you using ?

Thanks & regards
Leo

[karnanl]

Hello Luigi @maggilgi

Although it not mentioned in our PG232, it seems our developer team also tested our MIPI CSI-2 RX IP using Zybo Z7 resistive circuit without any issue.

https://reference.digilentinc.com/reference/programmable-logic/zybo-z7/start
https://reference.digilentinc.com/_media/reference/programmable-logic/zybo-z7/zybo_z7_sch-public.pdf
https://reference.digilentinc.com/reference/programmable-logic/zybo-z7/reference-manual

Zybo Z7 has resistor-network exactly the same configuration as mentioned in XAPP894.

Thanks & regards
Leo

[florentw]

HI @maggilgi,

Do you have any updates on this? Was @karnanl's reply enough for you?

If your question is answered or your issue is solved, please kindly mark the response which helped as solution (click on "Accept as solution" button below the reply)

If this is not solved/answered, please reply in the topic giving more information on your current status.

Thanks and Regards,