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jiaohuang2004
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Registered: ‎09-22-2020

MIPI CSI2 TX debug

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Using Vivado 2019.1 in Windows 10 64-bit, I using the Xilinx MIPI CSI-2 Tx Subsystem (2.0).

Video stream resolution: 3840 X2160 10fps.

Video stream including line and field blanking resolution is 5888 x 4704

The input Mipi video stream signal is as follows

The register information is as follows 

0x80000000(0x0)  :0x00000005

0x80000004(0x04):0x0000001B

0x80000024 (0x24):0x00000000

The overall register information is as follows

0x80000000 : 0x80000000 <Hex Integer>
       Address                0 - 3         4 - 7         8 - B          C - F
0000000080000000 00000005 0000001B 00000000 00000000
0000000080000010 00000000 00000000 00000000 00000000
0000000080000020 00000001 00000000 00000000 00000000
0000000080000030 00000000 00000000 00000000 00000000
0000000080000040 00000000 00000000 00000000 00000000
0000000080000050 00000000 00000000 00000000 00000000
0000000080000060 00000000 00000000 00000000 00000000
0000000080000070 00000000 00000000 00000020 00000000

Problem: there is no frame start and end signal in Mipi timing sequence, which is always periodic line data. You can refer to the actual waveform of oscilloscope in the figure below

 

 

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jiaohuang2004
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Registered: ‎09-22-2020

Good news, when I changed to native mode and input the correct line and frame timing, the frame spacing in Mipi TX appeared!

I think there is no obvious frame interval time in stream mode, so the output can hardly see the frame interval time.

I think all the advices provided by you are helpful!  It speeds up the solution to this problem. Thank you very much!

View solution in original post

9 Replies
karnanl
Xilinx Employee
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Registered: ‎03-30-2016

Hello @jiaohuang2004 

1. I cannot check your waveform at this level but I believe your TUSER[0] input timing is not correct.
    Please see waveform shown at PG260 Figure B2.
   TUSER[0] should be asserted for 1 s_axis_aclk at the first pixel of the first line.
   PG260_Figure_B2.png

2. Since you enabled "Enable Register Based Frame Generation" option,
    Please configure Line Count register correctly for all VC.
    Enable_reg_based_FE_gen.png

Thanks & regards
Leo


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jiaohuang2004
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Thank you for your reply. Since the tuser signal is from the previous scaling IP, this IP was written by myself in HLS. I will focus on checking this module, but this module runs successfully on the platform of zynq7030
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jiaohuang2004
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Today, I experimented on the zynq 7030 platform. Although tuser0 is still very wide, it works normally because the video output to HDMI can be displayed normally.

Because the output needs precise timing control (row blanking and field blanking), do I need native mode?

Because the total resolution (including line blanking and field blanking time) is 5888x4704, if I need native mode, do I need to write VHDL support myself, because VTC should not support such a high resolution.

I have configured the line count register, but it does not work properly, because 0x40 is always zero. Here is my initialization code. Is it correct?

 

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karnanl
Xilinx Employee
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Registered: ‎03-30-2016


Hello @jiaohuang2004 

I am a bit puzzled with your explanation above.

>Today, I experimented on the zynq 7030 platform. Although tuser0 is still very wide, it works normally because the video output to HDMI can be displayed normally.

Are you using MIPI CSI-2 TX in your ZYNQ 7030 platform ? ( If this is a system with HDMI TX then this information is unrelated )

Looking at your waveform :
HUANG_waveform.png

1. What is TID ? Why it is always low ?
    Did you set MIPI CSI-2 DataType (tuser[6:1]) correctly ?

2. Could you please zoom and share the waveform of the first line ?
    (I need to confirm if PG260 Figure B2 guidance is adhered correctly. )

>Because the output needs precise timing control (row blanking and field blanking), do I need native mode?

AXI4-stream mode is much easier to use compared to Native-mode. I would recommend most user to use AXI4-stream mode.
# But if your Sink/Receiver needs a precise timing control. Native mode is the only choice.
   Could you please share a simple diagram of your system  ? Why would you need to use MIPI CSI-2 TX Subsystem ?

Thanks & regards
Leo


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jiaohuang2004
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Thank you for your reply. The system description is shown in the following block diagram

This is a block diagram of the normal operation of the system. Now to replace the CMOS part, we need to simulate the behavior of CMOS to test the image processing platform. So the block diagram looks like this

The interface between CMOS and image processing platform is mipi, so it is necessary to simulate mipi TX in FPGA.

The parameters of CMOS are as follows:

Row active pixels          : 3840

frame of active lines     : 2160

Line blanking  : 2048

Frame blanking : 2544

 

1 The ZYNQ 7030 platform is HDMI IN and HDMI out but the module input to Mipi and HDMI is the same.

2 Tid is the scaler which using HLS TID signal is in the scaling module, which is written by the HLS, I think this signal can be ignored.

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karnanl
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Registered: ‎03-30-2016

Hello @jiaohuang2004 


>1 The ZYNQ 7030 platform is HDMI IN and HDMI out ,but the module input to Mipi and HDMI is the same.
>2 Tid is the scaler which using HLS TID signal is in the scaling module, which is written by the HLS, I think this signal can be ignored.

Noted. Thanks for sharing this.
(So, the previous working system is using HDMI RX-->HDMI TX. Not related with MIPI CSI-2 TX)

No_issue_on_TUSER0.png

I do not see any issue with TUSER[0] asertion above.

REG_no_issue.png
I do not see any issue with MIPI CSI-2 TX Subsystem register dump.


1. How did you set DataType and WordCount ?
2. How do you know that MIPI CSI-2 TX subsystem does not send any frame-start/frame-end ? Are you using MIPI CSI-2 analyzer ?
3. Since you enabled "Enable Register Based Frame Generation" option, number of line (reg offset 0x40) should be set as 2160.
   ( No need to set offset 0x44, 0x48, 0x4C if your system is using VC0 only )
   # Or as an alternative , you can disable "Enable Register Based Frame Generation" option, so MIPI CSI-2 TX can generate Frame-End packet automatically, before sending the next Frame-Start packet.
4. Is pl_clk0 clock frequency =200MHz ?
5. Did you reset MIPI CSI-2 TX after you can confirm 200MHz clock is running stable ?
6. Could you please check if mmcm_lock_out=1, pll_lock_out=1 ?

Thanks & regards
Leo


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jiaohuang2004
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  1. How did you set DataType and WordCount ?

   DataType = 0x2C   RAW12  However, in the initialization structure(config

), the default value is 0x0a

   WordCount = 0x1680 3840X12/8

2 How do you know that MIPI CSI-2 TX subsystem does not send any frame-start/frame-end ? Are you using MIPI CSI-2 analyzer ?

 NoI am not using MIPI CSI-2 analyzer. I saw it on the oscilloscope .The oscillograph is full of periodic line signals, without periodic frame signals (frame signals should have LP11 with long interval)

3 Since you enabled "Enable Register Based Frame Generation" option, number of line (reg offset 0x40) should be set as 2160.
   ( No need to set offset 0x44, 0x48, 0x4C if your system is using VC0 only )
   # Or as an alternative , you can disable "Enable Register Based Frame Generation" option, so MIPI CSI-2 TX can generate Frame-End packet automatically, before sending the next Frame-Start packet.

  Yes, I will do it

 

  1. Is pl_clk0 clock frequency =200MHz ?

  Yes, PL_CLK0 200MHz, Maybe 199.9980001MHz. This is the clock for Mipi dphy

The mipi tx communication rat is 936Mbps/laneso mpi tx module s_axis_aclk = 312MHz Maybe 311.997MHz.

5. Did you reset MIPI CSI-2 TX after you can confirm 200MHz clock is running stable ?
6. Could you please check if mmcm_lock_out=1, pll_lock_out=1 ?

Yes,I will do it

jiaohuang2004
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Registered: ‎09-22-2020

Good news, when I changed to native mode and input the correct line and frame timing, the frame spacing in Mipi TX appeared!

I think there is no obvious frame interval time in stream mode, so the output can hardly see the frame interval time.

I think all the advices provided by you are helpful!  It speeds up the solution to this problem. Thank you very much!

View solution in original post

karnanl
Xilinx Employee
Xilinx Employee
642 Views
Registered: ‎03-30-2016

Hello @jiaohuang2004 

Thank you for updating this thread.

1. Great job for using Native interface in such a short period of time.
   # Most user will most likely struggle to input the correct data rate at first.
      So, ISR will show either "Line buffer full" or "Pixel Data under-run"

2. "I think there is no obvious frame interval time in stream mode, so the output can hardly see the frame interval time"
    With AXI4-stream I/F, MIPI CSI-2 TX will send first pixel data, after sent FS short packet.
    ( So, if your RX/Sink has a timing requirement beyond MIPI CSI-2 spec, native interface is your only choice )

Regards
Leo


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