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Visitor
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Registered: ‎09-07-2019

MIPI D-PHY(v3.0) txreadyhs

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I used mipi dphy in VCU118 xilinx FPGA board. Found the 4 lanes txreadyhs is not aligned.  

Now my mipi controller is one input port for txreadyhs. 

How used it.

Pease give me some advance. thank you ~

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Xilinx Employee
Xilinx Employee
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Registered: ‎03-30-2016

Hello @lxxu 

Your MIPI D-PHY IP version is too old . It is generated from Vivado 2016.3 ( which is no longer supported Vivado version)
The behavior is expected txreadyhs when using  MIPI D-PHY IP (ver3.0). This bug is fixed on 2017.4

2017.4:
* Version 4.0 (Rev. 1)
* Bug Fix: Fixed treadyhs assertion across lanes in D-PHY Tx
* Bug Fix: HS_PREPARE duration fixed to be within specification limits for 7-Series MIPI D-PHY Tx with OBUFTDS enabled
* Feature Enhancement: Support for Virtex7,Kintex7,Artix7,Zynq-7000 devices at Production status
* Other: Updated HSSIO DIFFERENTIAL_IO_TERMINATION parameter from NONE to TERM_NONE

 

Please use the latest IP from 2019.2

Thanks & regards
Leo

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Xilinx Employee
Xilinx Employee
355 Views
Registered: ‎03-30-2016

Hello @lxxu 

Your MIPI D-PHY IP version is too old . It is generated from Vivado 2016.3 ( which is no longer supported Vivado version)
The behavior is expected txreadyhs when using  MIPI D-PHY IP (ver3.0). This bug is fixed on 2017.4

2017.4:
* Version 4.0 (Rev. 1)
* Bug Fix: Fixed treadyhs assertion across lanes in D-PHY Tx
* Bug Fix: HS_PREPARE duration fixed to be within specification limits for 7-Series MIPI D-PHY Tx with OBUFTDS enabled
* Feature Enhancement: Support for Virtex7,Kintex7,Artix7,Zynq-7000 devices at Production status
* Other: Updated HSSIO DIFFERENTIAL_IO_TERMINATION parameter from NONE to TERM_NONE

 

Please use the latest IP from 2019.2

Thanks & regards
Leo

View solution in original post

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Visitor
Visitor
341 Views
Registered: ‎09-07-2019
hi karnanl,
well, i will try it.
You've helped me a lot. thank ypu~
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