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beandigital
Scholar
Scholar
492 Views
Registered: ‎04-27-2010

MIPI RX issue using Spartan 7

I am trying to get a MIPI RX design working with Spartan 7. I have 4 lanes working at 800Mbps. I have setup the IP with 4 pixels per clock and an 80MHz video clock. The video input is a 1080P60 with 10-bit RAW pixels. 

If I have tried with both the register and non register interface. In both modes I see no errors generated but there are no packets received either (see below). 

The FPGA is connected to a TI deserialiser using the XAPP894 resistor network. I am using LVDS25 for the HS and HSUL12 for the LS inputs. 

Can anyone suggest anything else that I can check? Thanks 

Untitled.png

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10 Replies
watari
Teacher
Teacher
470 Views
Registered: ‎06-16-2013

Hi @beandigital 

 

Do you connect 200[MHz] as reference clock to MIPI D PHY ?

 

Best regards,

karnanl
Xilinx Employee
Xilinx Employee
427 Views
Registered: ‎03-30-2016

Hello @beandigital 

1. Could you please share the following MIPI D-PHY IP register value ?
      0x0 : CONTROL Register
      0x4 : IDELAY_TAP_VALUE
      0x18 : CL_STATUS for clock Lane.
      0x1C~0x28 : DL0_STATUS for data lanes 1 to 4.
 # I am suspecting either
    a. INIT_DONE is not asserted
    b. or clock/data lane are still in LP mode.

2. Could you please capture MIPI D-PHY input signal using oscilloscope ?
    # I want to check the scope waveform "during MIPI CSI-2 RX initialization period".
    # You need to ensure that sensor is not in HS mode and sending HS data, when you reset MIPI CSI-2 RX IP.

Kind regards
Leo


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beandigital
Scholar
Scholar
404 Views
Registered: ‎04-27-2010

Hi @watari Yes I can confirm that the 200MHz clock is connected

Hi @karnanl 

Below is the capture of the D-PHY registers. I have the calib set to auto mode

Untitled.png

I dont have a scope that has enough bandwidth to capture the MIPI waveforms with enough detail that would be useful. I have attached some images to give you some idea of what is happening on the bus

The image below shows one of the data lines. 

1.png

The image below shows the data line zoomed out

vid.png

Thanks

Jon

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karnanl
Xilinx Employee
Xilinx Employee
374 Views
Registered: ‎03-30-2016

Hello @beandigital 

1. Please see that INIT_DONE for clock lane and data lanes are all "0"
    INIT_DONE="0" means MIPI D-PHY RX IP cannot complete initialization process correctly, so MIPI D-PHY will not work.

    INIT_DONE_IS_NOT_ASSERTED.png

2. I cannot see "MIPI D-PHY reset timing" from your oscilloscope waveform.
   Please capture the waveform after board power-up, when you actually reset MIPI CSI-2 RX IP.
   # When you reset MIPI CSI-2 RX IP,  You need to ensure that sensor is not sending HS data,


Kind regards
Leo


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beandigital
Scholar
Scholar
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Registered: ‎04-27-2010

Hi @karnanl 

Thanks for the reply. But I am not sure how I can really capture the startup conditions that you want. I will need a much better scope with large memory store the capture. 

Should the IP be able to init under normal operating conditions? Or does the MIPI transmitter need to send some init sequence when its first powered up?

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beandigital
Scholar
Scholar
331 Views
Registered: ‎04-27-2010

Hi @karnanl 

I managed to capture the initialization state of the clock. It looks like its at least 10ms width. 

clk.png

 

beandigital
Scholar
Scholar
270 Views
Registered: ‎04-27-2010

Hi @karnanl 

I manged to get the init to work. I had to delay setting up the sensor until I had reset the MIPI IP. 

I am now getting video data. I had to increase the IDELAY tap values to get packets. But I have quite a few errors in the interrupt register. If I look at the video data it doesnt seem correct. The line length isn't what I expect (I get about 260 with 4 pixel per clock, but the video is 1920 so I expect 480) and I dont ever seem to get the TUSER asserted for the start of the frame.

Another thing is that if I stop the IP running, reset it, then start it I stop getting packets. Is this the expected behavior? The INIT done bit is still set in the clock status register. 

Untitled.png

karnanl
Xilinx Employee
Xilinx Employee
231 Views
Registered: ‎03-30-2016

Hello @beandigital 

>I manged to get the init to work. I had to delay setting up the sensor until I had reset the MIPI IP.  I am now getting video data.

Congratulation. INIT_DONE are asserted !

>I had to increase the IDELAY tap values to get packets. But I have quite a few errors in the interrupt register. If I look at the video data it doesnt seem correct. The line length isn't what I expect (I get about 260 with 4 pixel per clock, but the video is 1920 so I expect 480) and I dont ever seem to get the TUSER asserted for the start of the frame.

Noted.


BTW, What is the Vivado version you are using ? It seems you are using MIPI CSI-2 RX rather than MIPI D-PHY RX.


REG_DUMP_CSI.png
Confirmed your "MIPI CSI-2 RX register dump". It seems that these error flags are asserted
     ECC 2-bit error
     ECC 1-bit error
     SoT error
Perhaps you need to sweep IDELAY_TAP_VALUE for each lane to get the suitable setting.

>Another thing is that if I stop the IP running, reset it, then start it I stop getting packets. Is this the expected behavior? The INIT done bit is still set in the clock status register.

(a) When you stop the IP, did you also stop data from sensor ? ( So, sensor is sending LP-11 (Stop-State))
(b) If you have implemented two (or more) MIPI IPs in the same HP IO bank, could you please confirm if you reset both MIPI IPs at the same time ?
      See also : https://www.xilinx.com/support/answers/71374.html


Kind regards
Leo


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beandigital
Scholar
Scholar
214 Views
Registered: ‎04-27-2010

Hi @karnanl 

I am using Vivado 2020.1 and the MIPI RX IP with the D-PHY contained inside it. Do you think it would be easier to get the link working with just the D-PHY? It seems like it may be difficult to get each lane working on its own. 

When I reset the IP the sensor was still transmitting data. Are you saying that if I reset the sensor I have to then get the sensor to then start sensing LP-11 again?

Thanks

Jon

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karnanl
Xilinx Employee
Xilinx Employee
116 Views
Registered: ‎03-30-2016

Hello @beandigital 

>When I reset the IP the sensor was still transmitting data. Are you saying that if I reset the sensor I have to then get the sensor to then start sensing LP-11 again?

Yes, your understanding is correct.
If you need to restart data streaming, both sensor and MIPI CSI-2 RX (or MIPI D-PHY RX) need to be initialized.

Kind regards
Leo


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