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Contributor
Contributor
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Registered: ‎07-03-2018

Mipi Rx Subsystem - system reset output

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Hi there,

the Mipi RX Subsystem IP Core has a system_rst_out signal when containing the PLL/MMCM logic (master mode) 
I was wondering whether this output is just a forward of the video_aresetn or the lite_aresetn inputs or whether it can be pulled independently i.e. due to a lost PLL lock. Or in other words. Should the video_aresetn and/or the lite_aresetn be attached to the system_rst of the master or should it be an or combination of the global reset and the system_rst_out of the master? 

PG232 shows an example of a master driving several slaves but unfortunately the resets aren't connected at all in that example.

Regards,

Lenn

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Xilinx Employee
Xilinx Employee
806 Views
Registered: ‎03-30-2016

Hello Lenn @lennart_mle

system_rst_out is a basically an FSM output to indicate PLL reset is on progress. (system_rst_out=1 means PLL reset is asserted ), but this signal is no longer needed.
You have to reset all MIPI IP instances on the same bank at the same time.
( Please tied video_aresetn from all MIPI CSI-2 RX IP together )


Thanks & regards
Leo

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Xilinx Employee
Xilinx Employee
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Registered: ‎03-30-2016
Hello Lenn
PG232 is correct, you do not need to connect system_rst_out from master IP.
Please notice that there is no system_rst_in in the slave IP. ( It was exist on older version of IP )

Please tied video_aresetn from all MIPI CSI-2 RX IP together , you need to assert reset on all MIPI master & slave IP at the same time.
Please see also : https://www.xilinx.com/support/answers/68603.html

Thanks & regards
Leo
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Xilinx Employee
Xilinx Employee
873 Views
Registered: ‎03-30-2016

Hello Lenn @lennart_mle

Do you have any update on this ?
If you find my answer is enough for you. Could you please kindly mark this thread as Solved ?

Thanks
Leo

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Contributor
Contributor
844 Views
Registered: ‎07-03-2018

Hi Leo,

sorry I thought I replied already but I probably forgot to actually post it :/

Yes, your answer basically gives the feedback I need. I just wonder what exactly the system reset does than. Is it just an or connection of the two incoming resets or does it go high due to some internal states of the IP-Core i.e. PLL lock loss?

Regards,

Lenn

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Xilinx Employee
Xilinx Employee
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Registered: ‎03-30-2016

Hello Lenn @lennart_mle

system_rst_out is a basically an FSM output to indicate PLL reset is on progress. (system_rst_out=1 means PLL reset is asserted ), but this signal is no longer needed.
You have to reset all MIPI IP instances on the same bank at the same time.
( Please tied video_aresetn from all MIPI CSI-2 RX IP together )


Thanks & regards
Leo

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Moderator
Moderator
721 Views
Registered: ‎11-09-2015

Hi @lennart_mle,

Do you have any updates on this? Was the replies from @karnanl enough for you?

If your question is answered or your issue is solved, please kindly mark the response which helped as solution (click on "Accept as solution" button below the reply)

If this is not solved/answered, please reply in the topic giving more information on your current status.

Thanks and Regards,


Florent
Product Application Engineer - Xilinx Technical Support EMEA
**~ Don't forget to reply, give kudos, and accept as solution.~**
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