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Explorer
Explorer
178 Views
Registered: ‎06-13-2012

PetaLinux 2019.1 HDMI TX

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Hi all,

I'm designing a system based on a Zynq ultrascale+ with vivado and petalinux 2019.1, I want to generate a video signal in the PL and using the Xilinx HDMI tx subsystem "send it" to the screen.
I see that with petalinux the video bus must be 2 pixel per clock and if I understood it must be written and read from the processor ram.
It is possible to avoid passing through the processor ram and with petalinux just set up the HDMI/video PHY settings due to the video resolution? I don't need to elaborate the video signal.
Regards

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Moderator
Moderator
166 Views
Registered: ‎11-09-2015

HI @auricm 

I assume it might be possible to take the baremetal driver and create a kernel module (as this is just C code). But I am not sure how much effort is required for this


Florent
Product Application Engineer - Xilinx Technical Support EMEA
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Moderator
Moderator
171 Views
Registered: ‎11-09-2015

HI @auricm 

Not if you want to use the linux drivers. The HDMI TX subsystem linux driver is part of the DRM subsystem. And this is expecting to go from memory to the display. This is pretty much how linux is working (from and to memory).

So you might need to write your own driver (run the baremetal one from the userspace might work). Another solution could be to implement a microblaze in the PL to control the HDMI TX (and then find a way to communicate between the PS and the MB)


Florent
Product Application Engineer - Xilinx Technical Support EMEA
**~ Don't forget to reply, give kudos, and accept as solution.~**
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Explorer
Explorer
169 Views
Registered: ‎06-13-2012

Hi @florentw 

so I can use the driver used by microblaze and create a petalinux kernel module with that code?
Thank you 
Regards

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Moderator
Moderator
167 Views
Registered: ‎11-09-2015

HI @auricm 

I assume it might be possible to take the baremetal driver and create a kernel module (as this is just C code). But I am not sure how much effort is required for this


Florent
Product Application Engineer - Xilinx Technical Support EMEA
**~ Don't forget to reply, give kudos, and accept as solution.~**

View solution in original post