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Observer
Observer
1,589 Views
Registered: ‎05-24-2018

Pixel "shift" on a setup with Video Timing Controller and SII 9022 HDMI transmitter

Hello,

 

I'm working on a MYIR Z-Turn board with a Zynq 7020 and a SII 9022 HDMI transmitter, and I want to send video on a LCD 7" device, which has the following modeline (extracted from a Linux PC and parse-edid tool):

 

Modeline "Mode 0" 32.00 1024 1064 1112 1152 600 613 616 645 -hsync -vsync

 

The problem is that I get a vertical purple/pink line at the left (which seems to be 2 pixels wide) and I cannot set the 2 last pixels at the right of each line. If I try on a TV (Sony), I've the same behavior and the resolution is detected as "1026x600".

 

Here is a following very simplified diagram (I removed Framebuffer and Video Out IP to have the minimum blocks involved):

 

video_diagram.png

 

I set up the VTC as follows:

 

video_vtc_2.png

 

The FCLK0 clock is used as pixel clock and is set to 32 Mhz, as indicated by the EDID info.

Do I have to set specific constraints on the output ports (like timing constraints between data pins and the clock pin) ? I only set the PACKAGE_PIN and IOSTANDARD properties at the moment.

 

I'm not sure that the problem comes from the VTC, as there is the SII9022 in the path, but its programming is relatively straightforward (I set pixel clock, frame rate, total resolution). The SII9022 detects correctly the number of lines and the horizontal resolution from HSYNC/VSYNC.

 

Thanks in advance for any suggestion,

 

Christophe

 

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8 Replies
Teacher
Teacher
1,580 Views
Registered: ‎06-16-2013

Hi @cfillot

 

Would you change the HSYNC and VSYNC polarity in your design ?

Or

Would you change description of hsync and vsync polarity ?

 

Your design : (Maybe) HSYNC and VSYNC sync polarity is positive.

Your setting on X window : HSYNC and VSYNC sync polarity is negative.

 

Even if you change sync polarity, I suggest to change the following.

 

HSYNC polarity : negative

VSYNC polarity ; positive

 

[Additional content]

BTW, can this LCD panel support HTOTAL, VTOTAL and clock frequency are same as XGA (1024x768) video timing ?

If yes, I suggest to set XGA video timing except vertical active line (=600) on VTC ?

 

Best regards,

 

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Observer
Observer
1,555 Views
Registered: ‎05-24-2018

Hi @watari,

 

Thanks for your answer. I set HSync and VSync to Low polarity as indicated by the "-vsync" and "-hsync" in the modeline, but I will try your suggestion.

 

About the XGA video mode, the only reported modeline in EDID is this one (1024x600), but I can try that.

 

I tried different values for the Horizontal Sync Start and Sync End but this does not change anything, I guess the screen mainly rely on the DE signal to do its work (a hsync pulse is still required, but only to notify end of line).

 

Christophe

 

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Moderator
Moderator
1,496 Views
Registered: ‎11-09-2015

Hi @cfillot,

 

I am not sure about the clock from the EDID. Can you check what should be the refresh rate of the LCD monitor

 

If your total frame size is 1152*645 and you are running at 60 Hz your clock frequency should be 44,68MHz

 

1152*645*60 = 44,582,400 Hz

 

If your frequency is 32MHz your frame rate would be 43Hz which is a bit weird.

 

Maybe try with a different clock frequency just in case.

 

Hope that helps,


Florent
Product Application Engineer - Xilinx Technical Support EMEA
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Observer
Observer
1,491 Views
Registered: ‎05-24-2018

Hi @florentw,

 

Thanks for your answer. When I connect the screen to my PC it says that the refresh rate is indeed 43,1 Hz. I'll try with a pixel clock frequency of 44.68 Mhz.

 

I was wondering if my problem could be related to a timing issue between the pixel clock and hsync/vsync signals. The SII9022 manual gives a hold time of 2ns between the pixel clock and data signals, but I'm not really sure about how to do this.

 

Best regards,

 

Christophe

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Moderator
Moderator
1,487 Views
Registered: ‎11-09-2015

HI @cfillot,

 

Yes it might be related to timing as well. You might want to ask the question on the timing board. There are some great members who should be able to help you.

 

Regards,


Florent
Product Application Engineer - Xilinx Technical Support EMEA
**~ Don't forget to reply, give kudos, and accept as solution.~**
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Teacher
Teacher
1,473 Views
Registered: ‎06-16-2013

Hi @cfillot

 

Would you change the target vertical frequency to resolve timing closure from 60Hz to 50Hz ?

It's easy way to output video signal to TV or some monitor.

Because like PAL and so son require 25Hz/50Hz as vertical frequency.

TVs support it.

 

Best regards,

 

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Moderator
Moderator
1,403 Views
Registered: ‎11-09-2015

Hi Christophe @cfillot,

 

Were you able to make any progress on this? Did you try to add any constraints?

 

Regards,


Florent
Product Application Engineer - Xilinx Technical Support EMEA
**~ Don't forget to reply, give kudos, and accept as solution.~**
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Visitor
Visitor
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Registered: ‎01-06-2019

I had the same problem and was able to fix it by setting Sii9022 register 0x1a (CTRL_DATA) bit 0 to 0 (DVI) instead of 1 (HDMI). This made the 2 extra purple pixels per row go away on DVI monitors.