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Registered: ‎08-15-2017

Problem with configure Zynq ultrascale IO for HDMI out

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Hi. I create project for Zynq ultrascale with HDMI TX, but I cant assign data pins on ZCU102 boards. When I try set data line to a pin I give a message 

I cant copy it.

 

Code with serialization module below

 

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.std_logic_unsigned.all;

library UNISIM;
use UNISIM.VComponents.all;

entity OutputSERDES_v3 is
   Generic (
      kParallelWidth : natural := 10); -- number of parallel bits
   Port (
      PixelClk : in STD_LOGIC;   --TMDS clock x1 (CLKDIV)
      SerialClk : in STD_LOGIC;  --TMDS clock x5 (CLK)
      
      --Encoded serial data
      sDataOut_p : out STD_LOGIC;
      sDataOut_n : out STD_LOGIC;
      
      --Encoded parallel data (raw)
      pDataOut : in STD_LOGIC_VECTOR (kParallelWidth-1 downto 0);
      
      aRst : in STD_LOGIC);
end OutputSERDES_v3;

architecture Behavioral of OutputSERDES_v3 is

signal sDataOut, ocascade1, ocascade2 : std_logic;
signal pDataOut_q : std_logic_vector(13 downto 0);
signal shift_reg_n : std_logic_vector(4 downto 0);
signal shift_reg_p : std_logic_vector(9 downto 0);
signal cnt_ser     : std_logic_vector(3 downto 0);

begin

OBUFTDS_inst : OBUFTDS
   port map (
      O => sDataOut_p,   -- 1-bit output: Diff_p output (connect directly to top-level port)
      OB => sDataOut_n, -- 1-bit output: Diff_n output (connect directly to top-level port)
      I => sDataOut,   -- 1-bit input: Buffer input
      T => '0'    -- 1-bit input: 3-state enable input
   );

ODDR_inst : ODDR
   generic map(
      DDR_CLK_EDGE => "SAME_EDGE", -- "OPPOSITE_EDGE" or "SAME_EDGE" 
      INIT => '0',   -- Initial value for Q port ('1' or '0')
      SRTYPE => "ASYNC") -- Reset Type ("ASYNC" or "SYNC")
   port map (
      Q => sDataOut,   -- 1-bit DDR output
      C => SerialClk,    -- 1-bit clock input
      CE => '1',  -- 1-bit clock enable input
      D1 => shift_reg_p(8),  -- 1-bit data input (positive edge)
      D2 => shift_reg_p(9),  -- 1-bit data input (negative edge)
      R => aRst,    -- 1-bit reset input
      S => '0'     -- 1-bit set input
);

process(SerialClk)
begin
   if aRst = '1' then
      cnt_ser <= (others => '0');
   elsif rising_edge(SerialClk) then
      if cnt_ser >= 8 then
         cnt_ser <= (others => '0');
      else
         cnt_ser <= cnt_ser + "010";
      end if;
   end if;
end process;
process(SerialClk)
begin
   if rising_edge(SerialClk) then
      if cnt_ser = 0 then
         shift_reg_p <= pDataOut_q(13 downto 4);
      else
         shift_reg_p <= shift_reg_p(7 downto 0) & "00";
      end if;
   end if;
end process;


------------------------------------------------------------- 
-- Concatenate the serdes inputs together. Keep the timesliced
-- bits together, and placing the earliest bits on the right
-- ie, if data comes in 0, 1, 2, 3, 4, 5, 6, 7, ...
-- the output will be 3210, 7654, ...
-------------------------------------------------------------   
SliceOSERDES_q: for slice_count in 0 to kParallelWidth-1 generate begin
   --DVI sends least significant bit first 
   --OSERDESE2 sends D1 bit first
   pDataOut_q(14-slice_count-1) <= pDataOut(slice_count);
end generate SliceOSERDES_q;

end Behavioral;

Help me please.

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Moderator
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2,431 Views
Registered: ‎10-04-2017

HI ilyarromanenko@gmail.com and @andrew.kushchenko. Which reference design are you referencing?

Are you referencing the design from PG235 chapter 5 or some other design?

 

-Sam

 

 

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Xilinx Video Design Hub

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2,464 Views
Registered: ‎06-19-2018

Same here, T29-T30 cannot be assigned. However those pins are connected to HDMI. Reference design works, interesting, HOW ?

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2,432 Views
Registered: ‎10-04-2017

HI ilyarromanenko@gmail.com and @andrew.kushchenko. Which reference design are you referencing?

Are you referencing the design from PG235 chapter 5 or some other design?

 

-Sam

 

 

Don't forget to reply, kudo, and accept as solution.

Xilinx Video Design Hub

View solution in original post

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Registered: ‎11-09-2015

HI @andrew.kushchenko and ilyarromanenko@gmail.com

 

@samk is right on pointing you to the HDMI TX/RS subsystem example design.

 

I feel that you try to use the pin like normal IOs while these IOs are Gigabit Transceivers. To be used, the HDMI output requires the use of the HDMI IP and the video Phy. It is not like 7-series board having a ADV7511 which was "generating" the HDMI interface externally.


Florent
Product Application Engineer - Xilinx Technical Support EMEA
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2,400 Views
Registered: ‎06-19-2018

Hi, Thanks for pointing this out.

 

It is clear that on ZCU102 HDMI ports connecteed to GT pins, that cannot be instantiated. Thats nice, and now we have following options:

 

1. Buy Xilinx HDMI IP, by the way if you could point my where to license it, would be nice...

2. Use GTwizard to generate Tranciever , that has HDMI option, but how to use what is generated ? Any user guides ? examples ? Could not find anything informative yet....

 

I understand that you guys pushing everyone to buy HDMI IP from you, but what if we already have fully functional and working for our purpose HDMI IP's ? How to justify buying expensive IP, when we already have it, but cannot run it on your ultrascale device ? How to connect our HDMI IP to your (Xilinx) GT Tranciever ? 

 

 

Thanks in advance. Hope you can provide some useful information to reduce our engineering time and cost.

 

Ilya.

 

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Registered: ‎11-09-2015

Hi ilyarromanenko@gmail.com,

 

1. Buy Xilinx HDMI IP, by the way if you could point my where to license it, would be nice...

To buy a license for the Xilinx HDMI IP, you can an Authorized Distributor for your region

 

2. Use GTwizard to generate Tranciever , that has HDMI option, but how to use what is generated ? Any user guides ? examples ? Could not find anything informative yet....

You can use the Video phy which will instantiate the Transceiver for you (the video phy is free). However you still need to take care of the HDMI layer interface.

 

I understand that you guys pushing everyone to buy HDMI IP from you, but what if we already have fully functional and working for our purpose HDMI IP's ? How to justify buying expensive IP, when we already have it, but cannot run it on your ultrascale device ?

We are not pushing everyone to buy our HDMI IP. If you want to use your own, you can. However, we highly recommend to use our IP.

Then here remember that you are using the ZCU102 which is a Xilinx Evaluation Board. So we show that you can use HDMI for 4K (which you cannot do without using GTs) with Xilinx IPs. Most customers do not have their own IP and just want a plug and play solution. This is what we provide.

So if you want to use your own IP on US devices, you have few solution. Use our own board or your own external connector to interface the board.

 

How to connect our HDMI IP to your (Xilinx) GT Tranciever ?

Create an interface for your IP


Florent
Product Application Engineer - Xilinx Technical Support EMEA
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Registered: ‎06-19-2018

Hello,

 

I would be more than happy to use plug and play solution. Starting point would be of cause to compile example design. Unfortunately I cannot do that, because at this point your automated script tried to insert an IP, which I have to buy (even before try !).

 

Can I somehow get a  reference design, to understand how to use video_phy ?

 

We have HDMI layer interface, just need to connect it to video_phy... Plug and play would be nice, but it does not seem to be the case here...

 

image.png

image.png
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Registered: ‎11-09-2015

Hi ilyarromanenko@gmail.com,

 

The TPG is a free license. Just connect to your account.

 

You can also get a HW evaluation license for the HDMI IP if you want to evaluate it.

 

Note for the example design. I see that you are using windows. Make sure you are using a really short path to not hit the windows path limit.

 

Regards


Florent
Product Application Engineer - Xilinx Technical Support EMEA
**~ Don't forget to reply, give kudos, and accept as solution.~**
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2,360 Views
Registered: ‎06-19-2018

Hello,

 

Can you advice on eval licence magic ? 

 

I've cleaned the project after acquiring license, so that all IP's were regenerated, still I am not able to generate a bitstream.

 

Thank you in advance.

Ilya.

 

Capture-1.jpg

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Registered: ‎11-09-2015

HI ilyarromanenko@gmail.com,

 

Two things to try:

  • Could you try to recreate the design from scratch?
  • Could you make sure you are pointing to the directory for the HDMI license in XILINXD filed of Vivado License Manager
    lic.PNG

 


Florent
Product Application Engineer - Xilinx Technical Support EMEA
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Registered: ‎06-19-2018

Sorry but your suggestion did not help. I've setup environment variable and Licence manager now show the path, which is correct. You can also see the evaluation license, which is valid. 

 

Please help to get an example project compiled.

 

 

Thank you.

Ilya.

Capture-2.jpg

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Registered: ‎11-09-2015

Hi ilyarromanenko@gmail.com,

 

Did you start a complete new project?


Florent
Product Application Engineer - Xilinx Technical Support EMEA
**~ Don't forget to reply, give kudos, and accept as solution.~**
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Registered: ‎11-09-2015

HI ilyarromanenko@gmail.com,

 

What is your status on this? Were you able to use the HDMI example design as reference?


Florent
Product Application Engineer - Xilinx Technical Support EMEA
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Registered: ‎06-19-2018

Hello,

 

We can only compile reference project if we generate a new reference project from scratch.

 

We cannot istantiate components and use them, as it seems that you set some parameters and constants for your IP blocks from tcl differently compared to when it is added through IP catalogue.

 

Any comments ?

 

Ilya.

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Registered: ‎11-09-2015

Hi ilyarromanenko@gmail.com,

 

I am not sure to understand, could you explain more? Maybe with screenshots?


Florent
Product Application Engineer - Xilinx Technical Support EMEA
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Registered: ‎11-09-2015

Hi ilyarromanenko@gmail.com,

 

Do you have any updates on this?

 

Thanks,


Florent
Product Application Engineer - Xilinx Technical Support EMEA
**~ Don't forget to reply, give kudos, and accept as solution.~**
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