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Contributor
Contributor
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Registered: ‎03-11-2016

SLVS-EC on Ultrascale+ HP IO instead of tranceiver

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I intend to start this discussion as recent high resolution image sensors are migrating to SLVS-EC. This EC is embedded clock with 10b8b encoding for clock data recovery at the receiver end. It's still based on SLVS IO standard but running at 2.304Gbps per lane.

There's an existing IP from Framos 

https://www.xilinx.com/products/intellectual-property/1-yx5i51.html

And also for intel FPGA

https://www.macnica.com/americas/products/ip-software/slvs-ec-rx

Both appears to call for the internal gigabit tranceiver to do CDR.

 

Here's what appears to be interesting. The HP IO bank on most Ultrascale+ devices are capable of 2.5Gbps using MIPI-DPHY in the recent 2019.1 Update 1. The high speed mode of MIPI is essentially SLVS. Thus I wonder, if could use this IO standard to interface SLVS-EC without going for more expensive devices having dedicated transceivers. The strategy goes as follows:

1. FPGA MMCM generate 72MHz clock and 1.152GHz clock (x16)

2, 72MHz clock is forwarded to CMOS sensor to send out 2.304gbps SLVS-EC data at PLL x32

3. FPGA input using IBUFDS_DPHY with HS-only mode ( LPRX_DISABLE tie to VCC, HSRX_DISABLE tie to GND)

4. FPGA use internal RX_BITSLICE to center eye/capture data using synchornized native mode with 1.152GHz clock

5. 10/8b decoding in fabric and retrieve data for downstream

 

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Contributor
Contributor
340 Views
Registered: ‎03-11-2016

After several months I now come back with a better answer to my original question.

And yes, it's well possible and even on a 7 Series FPGA.

I do this as a hobby so I cannot afford expansive devices nor IP blocks.

BTW, 


@karnanl wrote:
  1. All UltraScale+ devices have a high-speed transceivers.
    If you are using UltraScale+ device, I do not see any benefit for NOT using the transceivers.

This is only true for ZU4 and above. ZU2/3 only has hardened GTR tranceiver, which resides on the PS side for PCIe/SATA/DisplayPort.

Here's my eye scan setup on Zynq 7010-C1 device. 72MHz oscillator clock is fanout on PCB to both FPGA MRCC and CIS sensor. Then MMCM generates a 576MHz BUFIO clock and 144MHz BUFR for data capture. IDELAYE2 is running at 52ps/300MHz refclk.

fshenmi_0-1599731181692.png

Note my connecor pins on my devkit are close to worn out so some lane usually requires reinserting to get better signal. This was observed on my other cameras at lower frequency.

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Xilinx Employee
Xilinx Employee
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Registered: ‎03-30-2016

Hello @fshenmi 

 

Hmm, This is an interesting idea. I do not say that it is impossible but, I think this is not worth the effort.

  1. All UltraScale+ devices have a high-speed transceivers.
    If you are using UltraScale+ device, I do not see any benefit for NOT using the transceivers.
  2. I see many customers using Xilinx transceiver (GTX/GTH) to receive SLVS-EC using various 3rd party IP. So this is a proven solution.
    Never see any customer using HP IO to receive SLVS-EC
  3. Before you start your design , something you need to consider are:
    (a) to design comma-align module and 8B10B decoding module using fabric that needs to be run at high speed (i.e 2304/10=230.4 MHz) It will require a lot of fabric area and timing closure effort.
    (b) HP IO does not have a built-in equalizer feature. (GTH/GTX do !)


Hope this helps.

Thanks & regards
Leo

Contributor
Contributor
341 Views
Registered: ‎03-11-2016

After several months I now come back with a better answer to my original question.

And yes, it's well possible and even on a 7 Series FPGA.

I do this as a hobby so I cannot afford expansive devices nor IP blocks.

BTW, 


@karnanl wrote:
  1. All UltraScale+ devices have a high-speed transceivers.
    If you are using UltraScale+ device, I do not see any benefit for NOT using the transceivers.

This is only true for ZU4 and above. ZU2/3 only has hardened GTR tranceiver, which resides on the PS side for PCIe/SATA/DisplayPort.

Here's my eye scan setup on Zynq 7010-C1 device. 72MHz oscillator clock is fanout on PCB to both FPGA MRCC and CIS sensor. Then MMCM generates a 576MHz BUFIO clock and 144MHz BUFR for data capture. IDELAYE2 is running at 52ps/300MHz refclk.

fshenmi_0-1599731181692.png

Note my connecor pins on my devkit are close to worn out so some lane usually requires reinserting to get better signal. This was observed on my other cameras at lower frequency.

View solution in original post

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