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radhen_17
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Registered: ‎10-17-2019

Share clock between two CSI-2 two lane port?

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Greetings,

I currently have the Ultra96 FPGA board from Xilinx. According to the documentation the board has one two lane CSI-2 port and one four lane CSI-2 port. My question is, is it possible to have an arrangement such that I can use one clock lane and the remaining six data lanes to connect three two lane cameras? If yes, then how should I go about programming it in the Vivado Design Suite software?

I was playing with the MIPI_CSI-2_Rx_Subsystem block in Vivado Design Suite the other day and I learned that I have an option to select one of the two CSI clock lanes present in Ultra96 board and based on those two clocks I can select a set of data lanes.

I am confused on how to go about connecting three two lane cameras with the Ultra96 board.

Looking forward to hearing your opinions/comments/suggestion. Thank you for reading.

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karnanl
Xilinx Employee
Xilinx Employee
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Registered: ‎03-30-2016

Hello @radhen_17 

1. Using US+ devices, a single HP bank can support up to eight @2lanes MIPI CSI-2 RX Subsystem IP.
    ( Please see PG232 Chapter 3, for IP connectivity to share the clock resources )
    PG232_multi_instances.png

2. If you want to implement 3 MIPI CSI-2 RX IPs, you need to connect clock lane individually.
    MIPI CSI-2 only support 1-to-1 connectivity. (see below)

    MIPI_3_inst.png

    ( The clock lanes need to be assigned on DBC/QBC/GC_QBC pins. I do not know if your sensor and Ultra96 board can support this, please check the documents yourself )

>do you know of any FPGA boards which would let me connect, say 4 cameras? 


3. ZCU102 should be good for this. It has  FMC connectors that connect to HP bank 65/66/67.
https://www.xilinx.com/support/documentation-navigation/design-hubs/dh0048-zcu102-evaluation-kit-hub.html


Regards
Leo

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karnanl
Xilinx Employee
Xilinx Employee
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Registered: ‎03-30-2016

Hello @radhen_17

Do you want to build a system like this ?
MIPI_SPLIT.png

If this is the case, I do not think this is possible. (The MIPI spec does not support this kind of connectivity ).

If you want to build a custom system , you are on your own.
You will need to synchronize each sensor with the "clock lane",
And ( from clock lane perspective ) all data lanes must satisfy setup/hold time requirement mentioned by the spec.


Regards
Leo

 

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radhen_17
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Registered: ‎10-17-2019

Thank you for the reply!

Yes, that is exactly what I had in mind.

Well, that's dissapointing. I was hoping to connect three cameras with the Ultra96 board.

On a side note, do you know of any FPGA boards which would let me connect, say 4 cameras? I know Jetson TX2 board from Nvidia has six 2-lane CSI ports. I am able to connect six cameras (OV5647) and stream images right now. I am getting a decent frame rate with 1980x1080 resolution. My goal is to compare the Jetson TX2 with a FPGA board.

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karnanl
Xilinx Employee
Xilinx Employee
762 Views
Registered: ‎03-30-2016

Hello @radhen_17 

1. Using US+ devices, a single HP bank can support up to eight @2lanes MIPI CSI-2 RX Subsystem IP.
    ( Please see PG232 Chapter 3, for IP connectivity to share the clock resources )
    PG232_multi_instances.png

2. If you want to implement 3 MIPI CSI-2 RX IPs, you need to connect clock lane individually.
    MIPI CSI-2 only support 1-to-1 connectivity. (see below)

    MIPI_3_inst.png

    ( The clock lanes need to be assigned on DBC/QBC/GC_QBC pins. I do not know if your sensor and Ultra96 board can support this, please check the documents yourself )

>do you know of any FPGA boards which would let me connect, say 4 cameras? 


3. ZCU102 should be good for this. It has  FMC connectors that connect to HP bank 65/66/67.
https://www.xilinx.com/support/documentation-navigation/design-hubs/dh0048-zcu102-evaluation-kit-hub.html


Regards
Leo

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aoifem
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Registered: ‎11-21-2018

Hi @radhen_17 

If your question is answered or your issue is solved, please kindly mark the response which helped as a solution (click on "Accept as solution" button below the reply).

 

If this is not solved/answered, please reply in the topic giving more information on your current status.

 

Thanks and Regards,

 

Aoife
Product Application Engineer - Xilinx Technical Support EMEA
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