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arulraj17993
Observer
Observer
681 Views
Registered: ‎11-15-2019

Supporting two mipi camera modules in xilinx ultra96v2 board.

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Hi,

We have a custom MIPI camera adapter board developed for xilinx community boards.

We could able to brinup and stream single MIPI camera using CN2 camera lines(CSI lines in HS exp header) as shown in the image below,

HS_EXP_HEADER.jpg

But when we try bringup two camera modules with both CN1 camera lines (DSI lines in HS exp header) and CN2 camera lines (CSI lines in HS exp haader) the device tree nodes are not properly generated.

Attached the generated pl.dtsi and modified system.dtsi and dmesg files in the "devicetree_files.zip.

When we analyzed the dmesg log, we observed the following error message,

[ 3.345113] xilinx-video amba_pl@0:vcap_mipi: parsing node /amba_pl@0/vcap_mipi
[ 3.352425] xilinx-video amba_pl@0:vcap_mipi: handling endpoint /amba_pl@0/vcap_mipi/ports/port@0/endpoint
[ 3.362091] xilinx-video amba_pl@0:vcap_mipi: xvip_graph_parse_one:415
[ 3.368614] xilinx-video amba_pl@0:vcap_mipi: xvip_graph_parse_one:429
[ 3.375134] xilinx-video amba_pl@0:vcap_mipi: handling endpoint /amba_pl@0/vcap_mipi/ports/port@1/endpoint
[ 3.384784] xilinx-video amba_pl@0:vcap_mipi: xvip_graph_parse_one:415
[ 3.391302] xilinx-video amba_pl@0:vcap_mipi: xvip_graph_parse_one:429
[ 3.397826] xilinx-video amba_pl@0:vcap_mipi: parsing node /amba_pl@0/mipi_csi2_rx_subsystem@bf000000
[ 3.407041] xilinx-video amba_pl@0:vcap_mipi: handling endpoint /amba_pl@0/mipi_csi2_rx_subsystem@bf000000/ports/port@0/endpoint
[ 3.418603] xilinx-video amba_pl@0:vcap_mipi: xvip_graph_parse_one:415
[ 3.425131] xilinx-video amba_pl@0:vcap_mipi: handling endpoint /amba_pl@0/mipi_csi2_rx_subsystem@bf000000/ports/port@1/endpoint
[ 3.436681] xilinx-video amba_pl@0:vcap_mipi: graph parsing failed
[ 3.443017] xilinx-video: probe of amba_pl@0:vcap_mipi failed with error -22

It seems we are configuring the device tree entry wrongly for the second camera module.

Can anyone please check our device tree entries and help us to solve the issue.

Note:

The CSI ports are not automatically generated for CN1 camera lines(please refer image). You can confirm it using "pl.dtsi" file attached. We dont know the reason fot it.

Thanks,

Koil Arul Raj.S

 

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karnanl
Xilinx Employee
Xilinx Employee
590 Views
Registered: ‎03-30-2016

Hello @arulraj17993 


> Do you find anything wrong in this approach?

I do not see any issue on this , since DSI_CLK_P/N is connected to QBC pins in ULTRA96 board.
So this DSI I/F can be used for MIPI CSI-2 RX inputs.
ULTRA96_DSI_CLK_is_assigned_on_QBC_pins.png

>Also is there any discrepency in our device tree configuration?

I do not think your vcap_mipi device entry in system-user.dtsi  is correct.

Could you please see the following link, to know how to define the MIPI node.
https://github.com/Xilinx/linux-xlnx/blob/master/Documentation/devicetree/bindings/media/xilinx/xlnx%2Ccsi2rxss.txt

Thanks & regards
Leo


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4 Replies
karnanl
Xilinx Employee
Xilinx Employee
634 Views
Registered: ‎03-30-2016

Hello @arulraj17993 

Looking at the picture you share here, I think CN1 is a MIPI interface for Display not for Camera Interface.
This_is_DSI_not_CSI.png

Regards
Leo


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arulraj17993
Observer
Observer
606 Views
Registered: ‎11-15-2019

Hi Leo,

Thanks for your response.

We have assigned DSI pins to CSI2 pins of MIPI CSI2 Rx subsystem block in the PL. Now could we able to connect the camera in those pins. Since those pins from HP bank of the zynq ultrascale device.

Do you find anything wrong in this approach?

Also is there any discrepency in our device tree configuration?

Thanks,

Koil Arul Raj.S

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karnanl
Xilinx Employee
Xilinx Employee
591 Views
Registered: ‎03-30-2016

Hello @arulraj17993 


> Do you find anything wrong in this approach?

I do not see any issue on this , since DSI_CLK_P/N is connected to QBC pins in ULTRA96 board.
So this DSI I/F can be used for MIPI CSI-2 RX inputs.
ULTRA96_DSI_CLK_is_assigned_on_QBC_pins.png

>Also is there any discrepency in our device tree configuration?

I do not think your vcap_mipi device entry in system-user.dtsi  is correct.

Could you please see the following link, to know how to define the MIPI node.
https://github.com/Xilinx/linux-xlnx/blob/master/Documentation/devicetree/bindings/media/xilinx/xlnx%2Ccsi2rxss.txt

Thanks & regards
Leo


------------------------------------------------------------------------------------------------

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If starting with Versal take a look at our Versal Design Process Hub and our
Versal Blogs

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View solution in original post

arulraj17993
Observer
Observer
534 Views
Registered: ‎11-15-2019

Hi Leo,

Yes. Configuring port for the second camera module in the same vcap_mipi property node was the issue. We have added separate vcap_mipi1 entry for the second camera module as follows to solve the issue.

&amba_pl {
    vcap_mipi1 {
        compatible = "xlnx,video";
        dma-names = "port0";
        dmas = <&mipi_csi2_rx_frame_buf_ipex_v_frmbuf_wr_0 0>;       
        ports {
            #address-cells = <1>;
            #size-cells = <0>;   
 
            port@0 {
                direction = "input";
                reg = <0>;
                vcap_mipi1_in: endpoint {
                    remote-endpoint = <&ipex_csiss_out>;
                };
            };
        };
    };
};
 
No we could able to stream both the camera module without any issues.
 
Thanks,
Koil Arul Raj.S
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